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    • 2. 发明专利
    • JPH05252084A
    • 1993-09-28
    • JP4580292
    • 1992-03-03
    • FUJITSU LTDNIPPON TELEGRAPH & TELEPHONE
    • TAKENAKA TETSUYOSHITOZAWA YOSHIHARUMISHIRO TOKIHIROKAZAMA HIROSHI
    • H04B1/04H04B7/15
    • PURPOSE:To attain the stable control of transmission power by controlling an increase rate of transmission power at a succeeding time so that a reception C/N estimated from the increasing rate of transmission power is equal to an actually measured C/N thereby generating control information with a small scale circuit. CONSTITUTION:An output of a transmission power control section 4 from a modulator 3 is sent to a satellite repeater 2 via an outdoor equipment 5, the equipment 5 receives its own station signal reflected in the repeater 2 and the signal is demodulated by a demodulator 6. A C/N conversion section 7 calculates the actually measured C/N from the demodulation output, and an arithmetic operation section 8 calculates information used for the control section 4 to control the transmission power at a succeeding time based on an increasing rate X of the transmission power at a current point of time at a fine weather and on the actually measured C/N. The arithmetic operation is implemented by including each of conditions such as rainfall attenuation quantities Lu, Ld, deterioration in reception C/N, a propagation time and a frequency of a radio wave for both up-link and down-link. Thus, control information is generated with a small scale circuit and stable control of transmission power is attained.
    • 3. 发明专利
    • CDMA COMMUNICATION SYSTEM
    • JPH06276176A
    • 1994-09-30
    • JP5845793
    • 1993-03-18
    • FUJITSU LTD
    • TAKENAKA TETSUYOSHIUSHIYAMA TAKAYUKIYAMASHITA ATSUSHI
    • H04B7/26H04J13/00H04W28/18H04W72/04
    • PURPOSE:To reduce intra-signal interference at the time of demodulating signals from respective remote stations and to solve a perspective problem by preparing plural chip rates and appropriately allocating them for the respective remote stations. CONSTITUTION:When the power level of reception signals initially detected by a reception power detection part 5 is as showh by a figure (b) for the signals from the remote stations RS1 and RS2 inputted to the spectrum inverse spread demodulation part 4 of a base station BS3, a chip rate deciding blade 6 judges that the reception power level of the RS1 is to be strong interference in the inverse spread demodulation of the signals of the RS2. Then, the present chip rate Cj of the RS1 is changed and decided to be Ci lower than the Cj and the RS1 is informed from a chip rate informing part 7. In the RS1, a spreading code is generated corresponding to the chip rate Ci informed from the BS by a spreading code generation part 8, is supplied to a spectrum spread modulation part 9 to perform spectrum spread modulation and is transmitted to the BS. Thus the reception power level from the RS1 and RS2 in the BS is turned to be as shown by the figure (c,) the BS performs an inverse spread processing by the chip rate Cj and the interference is reduced.
    • 6. 发明专利
    • MULTIPLIER CIRCUIT
    • JPH04149731A
    • 1992-05-22
    • JP27573990
    • 1990-10-15
    • FUJITSU LTD
    • YUDA TSUTOMUTAKENAKA TETSUYOSHIITO ETSUKO
    • G06F7/52G06F7/53G06F7/533
    • PURPOSE:To shorten the time for multiplication processing and to attain miniaturization of the multiplier circuit by obtaining the product of two numbers while performing one stage of correction processing. CONSTITUTION:The partial product of the negative expression of multiplicand and the most significant bit of multiplier by a first calculation means 111, and this partial product and the other partial product obtained by plural second calculation means 121 are added by an addition means 131. The addition result by this addition means 131 become equal to the result applying the correction to the direct product between the multiplicand and the multiplier. Therefore, the product between the multiplicand and the multiplier can be obtained by performing one stage of correction based on the output of the third calculation means 141 by a correction means 140. Thus, the time for multiplication can be shortened, and the miniaturization of the multiplier circuit can be attained.
    • 7. 发明专利
    • AUTOMATIC FREQUENCY CONTROL CIRCUIT
    • JPH03258057A
    • 1991-11-18
    • JP5609490
    • 1990-03-07
    • FUJITSU LTD
    • TAKENAKA TETSUYOSHIFURUKAWA HIDETO
    • H04L27/227H04L27/22
    • PURPOSE:To utilize respective advantages of a frequency discrimination type AFC circuit and a sweep type AFC circuit by receiving a frequency discrimination output whose offset is a prescribed level, giving a control output in the same locking direction to converge the frequency deviation to a voltage controlled oscillator so as to control the oscillated frequency. CONSTITUTION:An adder section 3 giving a prescribed offset epsilon to a discrimination output (d) of a frequency discriminator 2 is provided and a loop filter 4 controls the oscillating frequency of a VCO 5 so that a value (d+epsilon) converges a frequency deviation DELTAf between a reception signal frequency fin and the oscillated frequency fvco of the VCO 5 is converged. Since the frequency discrimination type AFC control and the sweep type AFC control coexist so as to provide a prescribed offset to an output of the frequency discriminator 2, a defect of the frequency discriminator AFC when the frequency fluctuation exceeds the transmission speed and a defect of the sweep type AFC requiring external control and possible for production of pseudo synchronization are compensated together.