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1. 发明专利

JP2014103540A Distortion compensation device, transmission device, distortion compensation method and transfer function calculation method 有权
标题翻译：失真补偿装置，变速装置，失真补偿方法和转移函数计算方法
公开(公告)号：JP2014103540A
公开(公告)日：2014-06-05
申请号：JP2012254360
申请日：2012-11-20
申请人： Fujitsu Ltd , 富士通株式会社
发明人： OISHI YASUYUKI , FUKUDA EISUKE , OHORA YOSHIMASA
IPC分类号： H03F1/32 , H03F3/24
CPC分类号： H03F1/3247 , H03F3/24 , H03F2201/3224 , H04L27/2614 , H04L27/368
摘要： PROBLEM TO BE SOLVED: To provide a distortion compensation device, a transmission device, a distortion compensation method and a transfer function calculation method that implement high performance distortion compensation with less computational complexity.SOLUTION: An amplifier module 6 is represented by a model having a first filter that is a linear time-invariant filter for limiting the band of an input signal, an amplification section for amplifying a signal output from the first filter, and a second filter that is a linear time-invariant filter for limiting the band of a signal output from the amplifier. A memoryless amplifier section 11 uses an AM/AM distortion and an AM/PM distortion of the amplification section to calculate an output of a memoryless version of the amplifier module 6. A cross-correlation operation section 13 calculates a cross-correlation between a signal output from the amplifier module 6 and the output calculated by the memoryless amplifier section 11, and on the basis of the result, calculates an estimate of a transfer function of the first filter and the second filter. A distortion compensation section 3 compensates an input signal on the basis of the estimate of the transfer function before outputting it to the amplifier module 6.
摘要翻译：要解决的问题：提供一种以较少的计算复杂度实现高性能失真补偿的失真补偿装置，发送装置，失真补偿方法和传递函数计算方法。解决方案：放大器模块6由具有第一滤波器，其是用于限制输入信号的频带的线性时间不变滤波器，用于放大从第一滤波器输出的信号的放大部分和作为用于限制第一滤波器的频带的线性时不变滤波器的第二滤波器信号从放大器输出。无记忆放大器部分11使用放大部分的AM / AM失真和AM / PM失真来计算放大器模块6的无记忆版本的输出。互相关运算部分13计算信号之间的互相关从放大器模块6输出的输出和由无记忆放大器部分11计算的输出，并且基于该结果，计算第一滤波器和第二滤波器的传递函数的估计。失真补偿部分3在将输出信号输出到放大器模块6之前，根据传递函数的估计来补偿输入信号。

2. 发明专利

JP2009219098A Communication apparatus 有权
标题翻译：通讯设备
公开(公告)号：JP2009219098A
公开(公告)日：2009-09-24
申请号：JP2008249105
申请日：2008-09-26
申请人： Fujitsu Ltd , 富士通株式会社
发明人： WU JIANMING , AZUMA MITSUHIRO , TANIGUCHI TOMOHIKO , FUKUDA EISUKE
IPC分类号： H04W52/24 , H04J1/00 , H04J11/00 , H04W24/10 , H04W52/30 , H04W72/04
CPC分类号： H04W52/143 , H04W16/10 , H04W16/12 , H04W52/241 , H04W52/243 , H04W52/38
摘要： PROBLEM TO BE SOLVED: To provide a communication apparatus capable of controlling the transmission power from a base station, without providing any particular communication channel, in fractional frequency reuse (FFR).
SOLUTION: Node-B transmits a power profile of each frequency of transmission data as a step function to a UE. Each UE measures the amount of interference of a received signal, evaluates SINR over the entire frequency band with the power of the received signal, and transmits the evaluation result to Node-B. Node-B evaluates the interference profile in Node-B from the information about the SINR transmitted from the UE and the power of the transmission signal, and determines the frequency profile of the power of the signal transmitted to the UE.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种在分数频率重用（FFR）中能够控制来自基站的传输功率而不提供任何特定通信信道的通信装置。解决方案：节点B向UE发送作为步进功能的每个发送数据频率的功率曲线。每个UE测量接收信号的干扰量，用接收信号的功率在整个频带上评估SINR，并将评估结果发送到节点B。节点B从关于从UE发送的SINR的信息和发送信号的功率的信息中评估节点B中的干扰简档，并且确定发送给UE的信号的功率的频率分布。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JPH0969733A AMPLIFIER HAVING DISTORTION COMPENSATION FUNCTION 失效
公开(公告)号：JPH0969733A
公开(公告)日：1997-03-11
申请号：JP22416995
申请日：1995-08-31
申请人： FUJITSU LTD
发明人： OISHI YASUYUKI , FURUKAWA HIDETO , HASE KAZUO , FUKUDA EISUKE , TAKANO TAKESHI
IPC分类号： H03F1/32
摘要： PROBLEM TO BE SOLVED: To reduce the capacity of a distortion compensation table and to eliminate the need for the polar/orthogonal and orthogonal/polar coordinate transformation operations by generating a compensation coefficient from the error signal obtained between the input signal and the output of an amplifier based on the adaptive algorithm to compensate the distortion characteristic component of the amplifier. SOLUTION: A compensation coefficient is generated from the error signal obtained between the input signal and the output of an amplifier 1 based on the adaptive algorithm to compensate the distortion characteristic component of the amplifier 1. That is, an estimated compensation coefficient generation circuit 50 applying the adaptive algorithm outputs a distortion compensation coefficient corresponding to the amplitude of a base band input signal X (t). Such coefficient uses a fact that it is equal to a function that is defined between the amplitude and phase distortions of the amplifier 1. Thereby, the circuit 50 has the distortion compensation coefficients corresponding to the input signal amplitude and the electric power or their functions. Then the signal X (t) is multiplied by the distortion compensation coefficient output of the circuit 50 by an amplifier 6.

4. 发明专利

JPH0555848A VARIABLE AMPLIFIER CIRCUIT 失效
公开(公告)号：JPH0555848A
公开(公告)日：1993-03-05
申请号：JP21251991
申请日：1991-08-26
申请人： FUJITSU LTD
发明人： FUKUDA EISUKE , OISHI YASUYUKI
IPC分类号： H03G3/10
摘要： PURPOSE:To miniaturize this variable amplifier circuit as an LSI by adding/ subtracting an output from a volume for inputting a signal to which a DC offset voltage is superposed as an input signal and an output from an electronic volume for inputting only the DC offset signal as an input signal to offset a change in the DC offset voltage. CONSTITUTION:An electronic volume(EV) 1 inputs an input signal (v+V) obtained by superposing a DC offset voltage V to a low frequency AC signal v and outputs an output voltage G(v+V) with variable gain G. An electronic volume(EV) 2 inputs only the voltage V as an input signal and outputs an output voltage GV with the same gain G. An adder/subtractor 3 adds/subtracts the outputs G(v+V) of the EV 1 and the output GV of the EV 2 and obtains an output signal V0=-Gv+V to offset a change in the voltage V. Since the V in the V0 becomes independent of the gain G of the EV 1 and EV 2, a fixed voltage is held. Thereby the generation of a change in the V can be prevented and a circuit appropriate for miniaturization and LSI formation can be obtained.

5. 发明专利

JPH0522356A MODULATOR 失效
公开(公告)号：JPH0522356A
公开(公告)日：1993-01-29
申请号：JP17503991
申请日：1991-07-16
申请人： FUJITSU LTD
发明人： ISHIKAWA ATSUKO , OISHI YASUYUKI , FUKUDA EISUKE
IPC分类号： H04L27/20
摘要： PURPOSE:To attain automatic adjustment by varying the adjustment quantity of a DC component level of a DC level adjustment means to minimize a carrier leakage for a pause period of burst transmission. CONSTITUTION:A carrier leak detection section 16 detects a carrier leak from a orthogonal modulator 13 for a pause period of burst transmission. Moreover, a comparator section 18 compares a carrier leak in the detection section 16 with a preceding carrier leak held in a holding section 17. A control section 19 varies an adjustment quantity of a DC component level of the DC level adjustment section 12 in response to the result of comparison. Then the level of the DC component is automatically adjusted to I and Q channel signals so as to minimize the carrier leakage for the pause period of burst transmission. Thus, a signal is sent in an excellent state with less carrier leakage in a succeeding time slot.

6. 发明专利

JPH04239808A AUTOMATIC GAIN CONTROL CIRCUIT 失效
公开(公告)号：JPH04239808A
公开(公告)日：1992-08-27
申请号：JP681091
申请日：1991-01-24
申请人： FUJITSU LTD
发明人： OISHI YASUYUKI , FUKUDA EISUKE
IPC分类号： H03G3/20 , H03G3/30
摘要： PURPOSE:To eliminate level fluctuation of a modulation wave due to Rayleigh fading without distorting an amplitude component of a reception modulation signal with respect to the automatic gain control circuit. CONSTITUTION:The automatic gain control circuit provided with a reception section 1 receiving a radio wave and sending a reception signal to an amplifier section 2, the gain variable amplifier section 2 amplifying the reception signal from the said reception section 1, a demodulation section 3 reproducing a code from the signal amplified by the said gain variable amplifier section 2, a detection section 5 receiving the signal amplified by the said gain variable amplifier section 2 and detecting the signal, and a filter section 7 controlling the gain based on the signal detected by the said detection section 5 is provided with a timing section 6 outputting a timing signal representing the timing to identify data based on the signal from the said demodulation section 3, and the said detection section 5 detects the said signal amplified in the identification timing represented by the said timing signal.

7. 发明专利

JPH03135252A SYNCHRONOUS DETECTION CIRCUIT 失效
公开(公告)号：JPH03135252A
公开(公告)日：1991-06-10
申请号：JP27351689
申请日：1989-10-20
申请人： FUJITSU LTD
发明人： FUKUDA EISUKE , OISHI YASUYUKI
IPC分类号： H03L7/08 , H04L27/22
摘要： PURPOSE:To attain synchronous detection with an optimum carrier phase by fixing a four-multiplication output in a state where it is continuously given to a voltage control oscillator at the time of synchronous detection, and switch- controlling a reference carrier by means of a two frequency-dividing clock as it is or between a pi/4 shift so as to attain orthogonal detection. CONSTITUTION:A phase error signal outputted from four-multiplier 5 through an orthogonal detector 3 and a filter 4 is given to the voltage control oscillator 7 at every two time slots. In such a state, a carrier reproduction loop 1 executes an orthogonal detection operation equal to a case when a QPSK modulation wave is received at every time slot. When the voltage control oscillator 7 is controlled and the carrier reproduction loop is synchronized, the output of a synchronous detection circuit 9 changes, a switching control circuit 10 fixes an on/off control signal CS2, fixes a sample holding circuit 6 to be an on-state and switches a switching circuit 8 by an on/off signal SC1 corresponding to the two frequency-dividing clock 2CLK at every time slot. Thus, synchronous detection is attained with the optimum carrier phase.

8. 发明专利

JPH02206906A LINEAR AMPLIFIER 失效
公开(公告)号：JPH02206906A
公开(公告)日：1990-08-16
申请号：JP2834289
申请日：1989-02-07
申请人： FUJITSU LTD
发明人： MINOWA MORIHIKO , FUKUDA EISUKE , TAKANO TAKESHI
IPC分类号： H03F1/02 , H03F1/32
摘要： PURPOSE:To improve the power efficiency by controlling an application voltage from a power supply circuit in response to a value corresponding to the amplitude of an input signal detected by an amplitude detector. CONSTITUTION:The amplitude of an input signal is detected by an amplitude detector 22 and the drain-source voltage of a transistor(TR) 21 is subject to variable control by a control circuit 24 and a power supply circuit 23. Thus, the drain-source voltage is controlled so as to be always in the saturation region with respect to the input level or the output level of the TR 21. Thus, the power efficiency of the amplifier is improved.

9. 发明专利

JPH0229264B2 失效
公开(公告)号：JPH0229264B2
公开(公告)日：1990-06-28
申请号：JP745484
申请日：1984-01-19
申请人： FUJITSU LTD
发明人： FUKUDA EISUKE , TAKEDA YUKIO , TAKENAKA SADAO
IPC分类号： H04L25/49 , H04L27/34 , H04L27/36 , H04L27/38

10. 发明专利

JPS6460133A CONTROL CIRCUIT FOR LOW FREQUENCY COMPONENT SUPPRESSION INTEGRATING VALUE 失效
公开(公告)号：JPS6460133A
公开(公告)日：1989-03-07
申请号：JP21742187
申请日：1987-08-31
申请人： FUJITSU LTD
发明人： FUKUDA EISUKE , YAMAGISHI MICHINAGA , AONO YOSHITAMI , MINOWA MORIHIKO , IWAMATSU TAKANORI , TAKENAKA SADAO
IPC分类号： H04L27/34 , H04L25/49 , H04L27/00
摘要： PURPOSE:To obtain a control means for low frequency suppression integrating value for facilitating the reproduction of a pilot carrier by adopting a modulating system to cause a space-arranged signal point to be unsymmetrical to the component axis or to cause a code allocation to the signal point not to be an inversion relation related to the component axis. CONSTITUTION:In-phase component data Iin and orthogonal component data Qin to be modulated are converted to corresponding component values (x) and (y) of a coordinates system for converting a code absolute value by a converting part 4 for the polarity deciding system. The components (x) and (y) are used for generating the sum for one frame at linear frame integration arithmetic circuits 6x and 6y, and for respective sums, polarity signals are outputted from polarity deciding circuits 8x and 8y. The polarity signal for converting the code absolute value is used for converting the I and Q components from one frame delaying parts 2I and 2Q by a code converting part 10. For frame outputs from the code converting part 10, a code converting flag is inserted to the frame slot by a flag inserting part 12. Thus, the low frequency component suppression integrating value control circuit to suppress a low frequency component can be obtained.

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