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1. 发明专利

JP4950407B2 有权
公开(公告)号：JP4950407B2
公开(公告)日：2012-06-13
申请号：JP2002525655
申请日：2001-09-06
IPC分类号： G10L19/00 , G10L19/02 , G10L19/14 , G11B20/00 , G11B20/10 , H03M3/02 , H03M7/30 , H04B14/06
摘要： Estimating a compression gain obtainable in compressing a given audio signal, comprising extracting a signal power in a selected frequency band of the given audio signal, and obtaining an estimation of the compression gain by correlation with the extracted signal power.

2. 发明专利

JP4093174B2 Reception apparatus and method 有权
公开(公告)号：JP4093174B2
公开(公告)日：2008-06-04
申请号：JP2003377339
申请日：2003-11-06
申请人：沖電気工業株式会社
发明人：厚史田代
IPC分类号： H04B14/06 , G10L19/00 , H04L29/08 , H04M1/00 , H04M3/00
CPC分类号： G10L19/005
摘要： A receiving device exhibits a high communication quality even if having a small time complexity and a small space complexity. The receiving receives a transmission unit signal sent from a sending device via a predetermined transmission path and executes a reproduction output corresponding to an element periodic signal that is a decoding result of the plurality of encoded element periodic signals extracted from the transmission unit signal. The receiving device detects a predetermined interference event to interfere with using of the encoded element periodic signals packed in the transmission unit signal for the reproduction output and interpolates an alternative element periodic signal into a series of element periodic signals.

3. 发明专利

JP3972000B2 adpcm speech coding system comprising a particular step size adaptation 有权
公开(公告)号：JP3972000B2
公开(公告)日：2007-09-05
申请号：JP2002580310
申请日：2002-03-25
申请人：コーニンクレッカフィリップスエレクトロニクスエヌヴィ
发明人：エルカンエフギギ
IPC分类号： G10L19/00 , H03M7/38 , H04B14/06
CPC分类号： H04B14/068 , G10L19/00
摘要： In a speech coding system with an encoder and a decoder cooperating with said encoder, the speech encoder comprises a pre-processor and an ADPCM encoder with a quantizer and step-size adaptation means, while the speech decoder comprises an ADPCM decoder with similar step-size adaptation means as in the ADPCM encoder and with a decoder, and a post-processor. The quantizer is provided with storage means containing values for a correction factor alpha(c(n)) of the step-size Delta(n), said correction factor being dependent on the quantizer output signal c(n). The step-size adaptation occurs in accordance with the relation: Delta ⁡ ( n + 1 ) = Delta ⁡ ( n ) . A . { alpha ⁡ ( c ⁡ ( n ) ) if ⁢ ⁢ alpha ⁡ ( c ⁡ ( n ) ) 1 alpha ⁡ ( c ⁡ ( n ) ) + b ⁢ if ⁢ ⁢ Delta ⁢ ⁢ ( n ) . A . c max Delta max 1 otherwise ⁢ .

4. 发明专利

JP3876781B2 Receiving apparatus and a receiving method, recording medium, and program 有权
公开(公告)号：JP3876781B2
公开(公告)日：2007-02-07
申请号：JP2002206469
申请日：2002-07-16
申请人：ソニー株式会社
发明人：正明服部 , 裕人木村 , 勉渡辺 , 岳歩福士 , 哲二郎近藤
IPC分类号： G10L19/00 , G10L19/06 , G10L19/08 , G10L19/16 , H04B7/26 , H04B14/06 , H04M1/00 , H04M1/725 , H04M3/42 , H04W4/16 , H04W88/02 , H04W88/14
CPC分类号： G10L21/038 , G10L21/0364
摘要： The present invention relates to a transmitting apparatus, a transmitting method, a receiving apparatus, a receiving method, a transceiver, a communication apparatus and method, a recording medium, and a program in which high quality voice can be decoded. A cellular telephone 421-1 outputs coded voice data and also supplies uncoded voice sample data to a switching center 423 while a telephone call is not made. Based on voice data used for the previous calculation processing and newly input voice data, the switching center 423 performs calculation processing for quality-improving data for improving the quality of voice to be output from a cellular telephone 421-2 that receives the coded voice data. The switching center 423 stores the optimal quality-improving data as a user information database in association with the cellular telephone 421-1. The cellular telephone 421-2 decodes the coded voice data based on the optimal quality-improving data supplied from the switching center 423. The present invention can be applied to cellular telephones.

5. 发明专利

JP3835822B2 A method and apparatus to generate a radio frequency signal 失效
公开(公告)号：JP3835822B2
公开(公告)日：2006-10-18
申请号：JP51354498
申请日：1997-08-26
申请人：テレフォンアクチーボラゲットエルエムエリクソン(パブル)
发明人：リチャードバージャーヘルバーグ，ラルス
IPC分类号： H03M3/02 , H04L27/20 , H03F3/24 , H04B14/06 , H04L25/03 , H04L25/49 , H04L27/36
CPC分类号： H03F3/24 , H03F2200/331 , H04L25/03834 , H04L27/362

6. 发明专利

JP3806344B2 Stationary noise segment detection device and a stationary noise interval detection method 有权
公开(公告)号：JP3806344B2
公开(公告)日：2006-08-09
申请号：JP2001367831
申请日：2001-11-30
申请人：日本電信電話株式会社 , 松下電器産業株式会社
发明人：和敏安永 , 祐介日和▲崎▼ , 宏幸江原 , 一則間野
IPC分类号： G10L11/02 , G10L19/08 , G10L11/06 , G10L19/12 , G10L19/14 , H04B14/06
摘要： PROBLEM TO BE SOLVED: To accurately detect a stationary noise signal section by discriminating between a stationary signal with periodicity and a stationary noise like white noise. SOLUTION: A 1st decision unit 121 temporarily decides whether a current process unit is a stationary noise section according to the result of a decision on the constancy of a decoded signal. A 2nd decision unit 124 further decides whether the current process unit is the stationary noise section according to the temporary decision unit and the decision result of the periodicity of the decoded signal and then correctly detects the stationary noise section while discriminating a decoded signal, such as a stationary vowel, included in a stationary voice signal from the stationary noise.

7. 发明专利

JP2005277759A Digital signal processor and digital signal processing method 有权
标题翻译：数字信号处理器和数字信号处理方法
公开(公告)号：JP2005277759A
公开(公告)日：2005-10-06
申请号：JP2004087721
申请日：2004-03-24
申请人： Sony Corp , ソニー株式会社
发明人： NOGUCHI MASAYOSHI , ICHIMURA HAJIME , SUZUKI NOBUKAZU
IPC分类号： G11B20/10 , G10L19/00 , G10L21/04 , G11B20/12 , H03M3/02 , H04B14/06
CPC分类号： H04B14/062
摘要： PROBLEM TO BE SOLVED: To achieve joining of 1-bit signals produced respectively at different sampling frequencies in an integer multiple relation to each other without causing noise. SOLUTION: Upon the receipt of a switching request signal 302, a controller 13 controls switching of a changeover switch 15 to provide an output of a switching output signal 305 resulting from smoothly selecting a 64fs rate reproduction signal 300, a 64fs cross fade signal 310 and then a 64fs mute pattern signal 308. When the 64fs mute pattern signal 308 is outputted, the controller 13 generates a switching signal 306 in a properly controlled timing to allow a mute pattern generator 12 to switch the 64fs mute pattern signal 308 into a 128fs mute pattern signal 309. A temporal average of a double integral signal with a minimum repetitive pattern is equal between the mute pattern signals of the two systems. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了实现分别以不同采样频率在整数倍关系中彼此产生而不产生噪声的1位信号的连接。解决方案：在接收到切换请求信号302时，控制器13控制切换开关15的切换，以提供由顺利选择64fs速率再现信号300而产生的切换输出信号305的输出，64fs交叉淡入淡出信号310，然后是64fs静音模式信号308.当输出64fs静音模式信号308时，控制器13以适当受控的定时产生切换信号306，以允许静音模式发生器12将64fs静音模式信号308切换成 128fs静音模式信号309.具有最小重复模式的双积分信号的时间平均在两个系统的静音模式信号之间相等。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP3513508B2 Recording and reproducing apparatus 有权
公开(公告)号：JP3513508B2
公开(公告)日：2004-03-31
申请号：JP2002121585
申请日：2002-04-24
申请人：シャープ株式会社
发明人：徹早瀬
IPC分类号： G10L19/00 , H04B14/06 , H04S1/00
摘要： PROBLEM TO BE SOLVED: To synthesize signals with a simple configuration and also to restore the original signal from the synthesized signal. SOLUTION: One-bit digital signals S1 (I) and S2 (I) outputted from signal sources 1 and 2 are synthesized by time division through the use of a prescribed time ratio in a time division signal synthesizing circuit 3 and, then, the synthetic signal S0 (I) is obtained. The time ratio is set by a gate timing control circuit 4.

9. 发明专利

JP2004056634A Signal processing apparatus, non-integral frequency divider and fractional n-phase lock loop synthesizer using the same 有权
$Signal processing apparatus, non-integral frequency divider and fractional n-phase lock loop synthesizer using the same$
公开(公告)号：JP2004056634A
公开(公告)日：2004-02-19
申请号：JP2002213888
申请日：2002-07-23
申请人： Nec Corp , 日本電気株式会社
发明人： MATSUNO NORIO
IPC分类号： H03K23/64 , H03L7/08 , H03L7/183 , H03L7/197 , H03M3/02 , H04B14/06
CPC分类号： H03L7/1976
摘要： PROBLEM TO BE SOLVED: To provide a signal processing apparatus with a small circuit scale, a non-integral frequency divider and a fractional N PLL (phase lock loop) synthesizer having the same. SOLUTION: An adder 8 and a delay device 10 constitute a 9-bit accumulator, output of an adder 2 is inputted and output of 3-input NAND gate 30 is connected with the remaining least significant bit input. An adder 13 and a delay device 15 constitute a 6-bit accumulator and output of the adder 8 is inputted. An adder 18 and a delay device 20 constitute a 4-bit accumulator and output of the adder 13 is inputted. Output of the delay device 20 is inputted in the 3-input NAND gate 30. Overflow signals 22 to 25 of each accumulator are inputted in a signal processing section 27, the sum of the overflow signal 22, first-order differentiation of the overflow signal 23, second-order differentiation of the overflow signal 24 and third-oder differentiation of the overflow signal 25 is obtained and the result is outputted from an output terminal 28. COPYRIGHT: (C)2004,JPO

10. 发明专利

JP3465401B2 Audio signal processing apparatus and audio recording device 失效
公开(公告)号：JP3465401B2
公开(公告)日：2003-11-10
申请号：JP4427195
申请日：1995-03-03
申请人：ソニー株式会社
发明人：康弘小倉 , 元市村 , 文孝西尾 , 誠阿久根
IPC分类号： G11B20/12 , G10L19/00 , G11B20/02 , G11B20/10 , H04B14/06
CPC分类号： G11B20/10527 , G11B20/02 , G11B20/10009 , G11B2020/00065

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