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1. 发明专利

JPH10173269A AUTOMATIC LIGHT POWER CONTROL CIRCUIT AND CONTROL SIGNAL GENERATING SECTION 失效
公开(公告)号：JPH10173269A
公开(公告)日：1998-06-26
申请号：JP32740096
申请日：1996-12-09
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： MATSUYAMA SATORU , MIKI MAKOTO , YASUDA SHUICHI , NOBECHI KIYOTOSHI , MURAKAMI NORIO , SHIMIZU KAZUYOSHI , AKAZAWA YUKIO , ISHIHARA NOBORU , NAKAMURA MAKOTO
IPC分类号： H01S5/06 , H01S3/103
摘要： PROBLEM TO BE SOLVED: To match the phase of a monitor voltage to that of a reference signal by setting the delay time of a delaying section to the sum of the delay time of a laser diode driving section and the light emission delay time of a laser diode. SOLUTION: The signal obtained by comparing an inversion signal and a non-inversion signal outputted from a data receiving signal 1 as the input signals of a laser diode driving section 2 is supplied to a reference voltage generating section 7 as a reference signal by delaying the signal by the time equal to the sum of the delay time of the driving section 2 and the light emission delay time of a laser diode 3. When the output signal of the data receiving section 1 is impressed upon the driving section 2, on the other hand, a monitor signal is outputted from a photodiode 4 with delay time which is equal to the sum of the delay time of the driving section 2 and the light emission delay time of the diode 3 and the outputs of the reference voltage generating section 7 and a monitor voltage generating section 8 simultaneously rise. Therefore, the output light level of the diode 3 becomes a prescribed value from the beginning of a burst signal and satisfies a pulse mask.

2. 发明专利

JPH1065459A CURRENT-VOLTAGE CONVERSION CIRCUIT 失效
公开(公告)号：JPH1065459A
公开(公告)日：1998-03-06
申请号：JP22082196
申请日：1996-08-22
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKAUJI TOSHIYUKI , MATSUYAMA SATORU , TAKEUCHI KOKEN , SHIMIZU KAZUYOSHI , AKAZAWA YUKIO , ISHIHARA NOBORU , NAKAMURA MAKOTO
IPC分类号： H03F1/30 , H03F3/08 , H03F3/34 , H03F3/347 , H04B10/40 , H04B10/50 , H04B10/60 , H04B10/67 , H04B10/69 , H04B10/04 , H04B10/06 , H04B10/14 , H04B10/26 , H04B10/28
摘要： PROBLEM TO BE SOLVED: To provide a wide dynamic range to an input and to allow the conversion circuit not to affected by fluctuation in temperature and power supply voltage and dispersion in the manufacture process by configuring a feedback resistor of an inverting amplifier with transistors(TRs) and applying a specific bias control signal to its control terminal. SOLUTION: A feedback resistor RF1 of an inverting amplifier A0 is made of a 1st TR T1. A power supply voltage V'0 depending on a prescribed constant voltage V0 is applied between channels of a 2nd TR T2 having the same characteristic as that of the 1st TR T1 and provides a prescribed current I0 . A bias control circuit (differential AMP1) generates a bias control signal BC2 to allow the TR 2 to generate a channel impedance RF2 equivalent to V'0 /I0 and the control signal BC2 is fed to control terminals of the TRs T1, T2 so that a relation of RF1 =RF2 is obtained and a prescribed resistance is obtained at all times.

3. 发明专利

JPH09162807A LASER LIGHT CONTROLLER, LIGHT SIGNAL TRANSMISSION DEVICE USING LASER LIGHT CONTROLLER, PEAK DETECTION DEVICE AND LIGHT SIGNAL TRANSMISSION/RECEPTION DEVICE 失效
公开(公告)号：JPH09162807A
公开(公告)日：1997-06-20
申请号：JP32069695
申请日：1995-12-08
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： MATSUYAMA SATORU , MURAKAMI NORIO , MIKI MAKOTO , CHIBA TAKAYA , SHIMIZU KAZUYOSHI , AKAZAWA YUKIO , ISHIHARA NOBORU , NAKAMURA MAKOTO
IPC分类号： G01J11/00 , H01S5/06 , H04B10/07 , H04B10/272 , H04B10/293 , H04B10/40 , H04B10/50 , H04B10/564 , H04B10/572 , H04B10/60 , H04B10/14 , H01S3/103 , H04B10/04 , H04B10/06
摘要： PROBLEM TO BE SOLVED: To provide a laser light controller which gradually suppresses the rise of output voltage while high speed rise time is secured and which can automatically control light output by providing plural specified differential amplifiers. SOLUTION: The first differential amplifier 4-1 receives a monitor signal and a reference signal and executes a comparison amplification operation. The second differential amplifier 4-2 executes an amplification operation corresponding to a difference between a monitor-side signal and a reference-side signal and the output is outputted to a charge control element 2 as the control signal of the charge control element 2. The gain of a third differential amplifier 4-3 is set larger than the second differential amplifier 4-2, and it receives the output of the first differential amplifier 4-1 and a laser light signal and executes the comparison/amplification operation. The output is outputted to an auxiliary element for charge control 3 as the control signal of the auxiliary element for charge control 3. A charge state to a charge circuit 1 is controlled by the charge control element 2 and the charge control element 2 is controlled by the auxiliary element for charge control 3.

4. 发明专利

JPH1065473A AMPLIFIER CIRCUIT 失效
公开(公告)号：JPH1065473A
公开(公告)日：1998-03-06
申请号：JP22081996
申请日：1996-08-22
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： SATO TSUTOMU , SHIMIZU KAZUYOSHI , YOITA MASAYUKI , AKAZAWA YUKIO , ISHIHARA NOBORU , NAKAMURA MAKOTO
IPC分类号： H03G11/00 , H03F1/30 , H03F3/34 , H03F3/45
摘要： PROBLEM TO BE SOLVED: To provide the amplifier circuit operated stably independently of the dispersion in the manufacture process, temperature, power supply fluctuation and presence of noise with respect to the amplifier circuit. SOLUTION: The amplifier circuit provided with an automatic threshold level setting circuit 10 that detects and holds a peak value Vp and a bottom value Vb of a burst signal Vi to generate an intermediate threshold level Vth and an amplitude limit amplifier circuit 20 amplifying the input signal Vi in a linear region around the threshold level Vth is provided with an offset compensation circuit 30 that applies feedback to the circuit 20 so as to obtain a prescribed level for the signal level based on an output signal V0 at non-signal so as to compensate a detection error in the threshold level Vth and other input offset component, and also with a comparator circuit 51 compares the detected peak level Vp or bottom level Vb with a prescribed reference level and with a clamp circuit T55 which clamps the output signal V0 to a prescribed level according to the comparison output and clamps the output signal V0 to a desired level when no burst is received.

5. 发明专利

JPH1065274A DRIVER FOR LIGHT-EMITTING ELEMENT 失效
公开(公告)号：JPH1065274A
公开(公告)日：1998-03-06
申请号：JP22082096
申请日：1996-08-22
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： NOBECHI KIYOTOSHI , MIKI MAKOTO , YASUDA SHUICHI , MATSUYAMA SATORU , MURAKAMI NORIO , KANESAKA HIROKAZU , AKAZAWA YUKIO , ISHIHARA NOBORU , NAKAMURA MAKOTO
IPC分类号： H01L33/00 , H01S5/00 , H01S5/068 , H03K17/78 , H01S3/18
摘要： PROBLEM TO BE SOLVED: To form a general purpose interface circuit by providing a high impedance threshold voltage generation circuit, where an interface circuit inputting a data signal is connected with each of a plurality of input terminals, and a circuit for comparing the data signal at respective input terminals. SOLUTION: An input interface circuit has two input terminals (a), (b), wherein one input terminal (a) is connected with a high impedance threshold voltage generation circuit A and the non-inverted input (+) of a comparison circuit CMP. The other input terminal (b) is connected with a high-impedance threshold voltage generation circuit B and the inverted input (-) of the comparison circuit CMP. Consequently, the input terminals (a), (b) are applied with predetermined threshold voltages Vth1 , Vth2 , respectively, and terminated with high impedances. An interface circuit having such a structure can interface with any type of input signal (unbalanced, balanced), thus realizing a general-purpose interface circuit.

6. 发明专利

JPS56115039A BINARY COUNTER 失效
公开(公告)号：JPS56115039A
公开(公告)日：1981-09-10
申请号：JP1733380
申请日：1980-02-15
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO , FUJITSU LTD
发明人： AKAZAWA YUKIO , KAWARADA KUNIYASU , HISHINUMA ESAO , MURATA MASANORI , IDE TETSUO , IWAMOTO HIROSHI
IPC分类号： H03K23/58 , H03K23/00
摘要： PURPOSE:To realize not only a high speed but a low power consumption with a simple constitution of circuit, by adding a D-FF and then applying the output of the D-FF to the reset input of the FF that forms a counter. CONSTITUTION:When the input pulse is applied through the terminal 1, FF1-FFn are turned on and off repetitively. Then NAND gate 3 is set at a low level when FF2-FFn are all set at a high level. In this case, if a fall is caused to the input signal, the D-FF reads the NAND output to turn to a low level. Thus the R signal is supplied to all FFs to start a resetting action. Then FF2-FFn are preset at the values designated by P2-Pn. And either one of P2-Pn is at a low level and read into the FF, and thus the output of the gate 3 is turned to a high level. When a fall occurs to the next input signal, the output of the gate 3 is read into the D-FF. Thus the D-FF turns to a high level to cancel the resetting action form. As a result, a delay equivalent to two units of FF has just to be given within an input period for the maximum operation speed. Thus a high speed and low power consumption can be realized.

7. 发明专利

JPH11355218A OPTICAL BURST CELL SIGNAL RECEPTION CIRCUIT 失效
公开(公告)号：JPH11355218A
公开(公告)日：1999-12-24
申请号：JP15640998
申请日：1998-06-04
申请人： NIPPON TELEGRAPH & TELEPHONE , NTT ELECTRONICS CORP
发明人： YOSHIDA SEISHI , AKAZAWA YUKIO , KUSAKA ATSUSHI , FUJISAWA TAKANORI
IPC分类号： H03F3/08 , H04B10/07 , H04B10/272 , H04B10/293 , H04B10/40 , H04B10/50 , H04B10/564 , H04B10/572 , H04B10/60 , H04B10/67 , H04B10/69 , H04B10/28 , H04B10/04 , H04B10/06 , H04B10/14 , H04B10/26
摘要： PROBLEM TO BE SOLVED: To provide an optical burst cell signal reception circuit which is highly sensitive and has a broad dynamic range. SOLUTION: An avalanche photodiode 1 as a photoelectric converter converts an inputted optical burst cell signal into a burst cell signal of an electric signal. An avalanche photodiode driving circuit 2 supplies the avalanche photodiode 1 with a bias voltage. A preamplifier 3 amplifies the burst cell signal from the avalanche photodiode 1. A level detection circuit 4 detects a voltage level of the amplified burst cell signal. An AGC circuit 5 which instantaneously responds and amplifies a voltage value of the burst signal to be inputted up to a specified voltage value. A discrimination/timing extraction IC 6 is composed of a discrimination circuit for discriminating whether a level of the signal is '1' or '0' and a timing extraction circuit for extracting a clock signal from the burst cell signal at high speed. A bypass circuit 7 is generated between terminals of the avalanche photodiode 1 and bypasses a charged and discharged current. A switch 8 connects an anode of the avalanche photodiode 1 to either the preamplifier 3 or the bypass circuit 7.

8. 发明专利

JPH0918525A DISCRIMINATING AND TIMING EXTRACTING CIRCUIT 失效
公开(公告)号：JPH0918525A
公开(公告)日：1997-01-17
申请号：JP18638395
申请日：1995-06-29
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： NAKAMURA MAKOTO , ISHIHARA NOBORU , AKAZAWA YUKIO
IPC分类号： H04L25/40 , H03L7/00 , H04L7/027 , H04L7/033
摘要： PURPOSE: To provide a discriminating and timing extracting circuit which can extract a clock from burst input data instantaneously and has small deviation between the extracted clock and optimum discrimination and timing even when the continuance of the same code of the burst input data is long. CONSTITUTION: The oscillation of a 1st voltage-controlled oscillator 4a is controlled with a 1st gating signal outputted by a 1st gating circuit equipped with a delay circuit, an exclusive OR circuit, and a logic inverting circuit. The discriminating and timing extracting circuit TC1 which discriminates the burst input data by a 1st discriminating circuit 5a according to the clock outputted by this 1st voltage-controlled oscillator 4a locks the phase of the clock by a PLL 11 and connects the oscillation frequency control terminal of the 1st voltage-controlled oscillator 4a and the oscillation frequency control terminal of a 2nd voltage-controlled oscillator 4a in the PLL 11 to the output terminal of a low-pass filter 7 in the PLL 11.

9. 发明专利

JPH01105605A WIDE BAND AMPLIFIER 失效
公开(公告)号：JPH01105605A
公开(公告)日：1989-04-24
申请号：JP18326788
申请日：1988-07-22
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： WAKIMOTO TSUTOMU , AKAZAWA YUKIO
IPC分类号： H03F3/45 , H03F1/34 , H03F1/48
摘要： PURPOSE:To make the band and the speed of a circuit wider and faster respectively by generating negative capacity in terms of a circuit, and canceling the junction capacity or the negative capacity of a transistor(TR), limiting the band of an amplification circuit. CONSTITUTION:In the circuit for canceling the input capacity Cin of the TR 5 or 6 (Miller capacity of inter-base-collector capacity and inter-base-emitter capacity), the TRs 33, 34 and a compensating capacity 35 constitute a capacity compensation circuit. The collector potential difference of the TRs 5, 6 is detected by the TRs 27, 28 constituting an emitter circuit, and the potential difference is impressed to the both ends of the capacity 35 through the TRs 33, 34, and is converted into a current. Since the current flows in Cin from the capacity compensation circuit, and if the value of the compensating capacity 35 and the voltage gain of a differential amplifier are assumed to be C1 and G respectively, Cin is canceled, and the working band of the differential amplifier can be widened, by selecting the value of C1 so that the input capacity value Cin of the TRs 5, 6 comes equal to 2G1.C1.

10. 发明专利

JPS63129704A HIGH SPEED AND HIGHLY ACCURATE BUFFER AMPLIFIER 失效
公开(公告)号：JPS63129704A
公开(公告)日：1988-06-02
申请号：JP27618386
申请日：1986-11-19
申请人： ADVANTEST CORP , NIPPON TELEGRAPH & TELEPHONE
发明人： NAKATANI TAKAYUKI , SHIBAZAKI HARUYUKI , AKAZAWA YUKIO , SHINAGAWA MITSURU
IPC分类号： H03F3/50 , H03F3/34
摘要： PURPOSE:To obtain a high speed highly accurate buffer amplifier provided with a low distortion factor by adding a current compensation circuit always compensating a current flowing to an active element to be constant in response to the change in a voltage given to a load of an emitter of the active element being a component of an emitter amplifier. CONSTITUTION:The current compensation circuit 5 is connected to the emitter of the active element 2. When a current flowing to the active element 2 is increased and its output voltage changes, a current flowing to a load 4 is changed. The output voltage change is given to a base of a transistor (TR) 6 via a level shift circuit 8 and a current flows to a dummy load 11. In selecting the impedance of the load 4 equal to the impedance of the dummy load 11, since the increment of the current flowing to the load 4 and the decrement of the collector current of a TR 7 are equal and the current through the active element 2 is unchanged. Thus, the current is always kept to a prescribed value independently of the excitation of the signal in the active element 2 and the mutual conductance (gm) and the current amplification factor beta are kept constant, then the distortion factor is improved.

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