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1. 发明专利

JPH11355218A OPTICAL BURST CELL SIGNAL RECEPTION CIRCUIT 失效
公开(公告)号：JPH11355218A
公开(公告)日：1999-12-24
申请号：JP15640998
申请日：1998-06-04
申请人： NIPPON TELEGRAPH & TELEPHONE , NTT ELECTRONICS CORP
发明人： YOSHIDA SEISHI , AKAZAWA YUKIO , KUSAKA ATSUSHI , FUJISAWA TAKANORI
IPC分类号： H03F3/08 , H04B10/07 , H04B10/272 , H04B10/293 , H04B10/40 , H04B10/50 , H04B10/564 , H04B10/572 , H04B10/60 , H04B10/67 , H04B10/69 , H04B10/28 , H04B10/04 , H04B10/06 , H04B10/14 , H04B10/26
摘要： PROBLEM TO BE SOLVED: To provide an optical burst cell signal reception circuit which is highly sensitive and has a broad dynamic range. SOLUTION: An avalanche photodiode 1 as a photoelectric converter converts an inputted optical burst cell signal into a burst cell signal of an electric signal. An avalanche photodiode driving circuit 2 supplies the avalanche photodiode 1 with a bias voltage. A preamplifier 3 amplifies the burst cell signal from the avalanche photodiode 1. A level detection circuit 4 detects a voltage level of the amplified burst cell signal. An AGC circuit 5 which instantaneously responds and amplifies a voltage value of the burst signal to be inputted up to a specified voltage value. A discrimination/timing extraction IC 6 is composed of a discrimination circuit for discriminating whether a level of the signal is '1' or '0' and a timing extraction circuit for extracting a clock signal from the burst cell signal at high speed. A bypass circuit 7 is generated between terminals of the avalanche photodiode 1 and bypasses a charged and discharged current. A switch 8 connects an anode of the avalanche photodiode 1 to either the preamplifier 3 or the bypass circuit 7.

2. 发明专利

JPH0918525A DISCRIMINATING AND TIMING EXTRACTING CIRCUIT 失效
公开(公告)号：JPH0918525A
公开(公告)日：1997-01-17
申请号：JP18638395
申请日：1995-06-29
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： NAKAMURA MAKOTO , ISHIHARA NOBORU , AKAZAWA YUKIO
IPC分类号： H04L25/40 , H03L7/00 , H04L7/027 , H04L7/033
摘要： PURPOSE: To provide a discriminating and timing extracting circuit which can extract a clock from burst input data instantaneously and has small deviation between the extracted clock and optimum discrimination and timing even when the continuance of the same code of the burst input data is long. CONSTITUTION: The oscillation of a 1st voltage-controlled oscillator 4a is controlled with a 1st gating signal outputted by a 1st gating circuit equipped with a delay circuit, an exclusive OR circuit, and a logic inverting circuit. The discriminating and timing extracting circuit TC1 which discriminates the burst input data by a 1st discriminating circuit 5a according to the clock outputted by this 1st voltage-controlled oscillator 4a locks the phase of the clock by a PLL 11 and connects the oscillation frequency control terminal of the 1st voltage-controlled oscillator 4a and the oscillation frequency control terminal of a 2nd voltage-controlled oscillator 4a in the PLL 11 to the output terminal of a low-pass filter 7 in the PLL 11.

3. 发明专利

JPH01105605A WIDE BAND AMPLIFIER 失效
公开(公告)号：JPH01105605A
公开(公告)日：1989-04-24
申请号：JP18326788
申请日：1988-07-22
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： WAKIMOTO TSUTOMU , AKAZAWA YUKIO
IPC分类号： H03F3/45 , H03F1/34 , H03F1/48
摘要： PURPOSE:To make the band and the speed of a circuit wider and faster respectively by generating negative capacity in terms of a circuit, and canceling the junction capacity or the negative capacity of a transistor(TR), limiting the band of an amplification circuit. CONSTITUTION:In the circuit for canceling the input capacity Cin of the TR 5 or 6 (Miller capacity of inter-base-collector capacity and inter-base-emitter capacity), the TRs 33, 34 and a compensating capacity 35 constitute a capacity compensation circuit. The collector potential difference of the TRs 5, 6 is detected by the TRs 27, 28 constituting an emitter circuit, and the potential difference is impressed to the both ends of the capacity 35 through the TRs 33, 34, and is converted into a current. Since the current flows in Cin from the capacity compensation circuit, and if the value of the compensating capacity 35 and the voltage gain of a differential amplifier are assumed to be C1 and G respectively, Cin is canceled, and the working band of the differential amplifier can be widened, by selecting the value of C1 so that the input capacity value Cin of the TRs 5, 6 comes equal to 2G1.C1.

4. 发明专利

JPS63129704A HIGH SPEED AND HIGHLY ACCURATE BUFFER AMPLIFIER 失效
公开(公告)号：JPS63129704A
公开(公告)日：1988-06-02
申请号：JP27618386
申请日：1986-11-19
申请人： ADVANTEST CORP , NIPPON TELEGRAPH & TELEPHONE
发明人： NAKATANI TAKAYUKI , SHIBAZAKI HARUYUKI , AKAZAWA YUKIO , SHINAGAWA MITSURU
IPC分类号： H03F3/50 , H03F3/34
摘要： PURPOSE:To obtain a high speed highly accurate buffer amplifier provided with a low distortion factor by adding a current compensation circuit always compensating a current flowing to an active element to be constant in response to the change in a voltage given to a load of an emitter of the active element being a component of an emitter amplifier. CONSTITUTION:The current compensation circuit 5 is connected to the emitter of the active element 2. When a current flowing to the active element 2 is increased and its output voltage changes, a current flowing to a load 4 is changed. The output voltage change is given to a base of a transistor (TR) 6 via a level shift circuit 8 and a current flows to a dummy load 11. In selecting the impedance of the load 4 equal to the impedance of the dummy load 11, since the increment of the current flowing to the load 4 and the decrement of the collector current of a TR 7 are equal and the current through the active element 2 is unchanged. Thus, the current is always kept to a prescribed value independently of the excitation of the signal in the active element 2 and the mutual conductance (gm) and the current amplification factor beta are kept constant, then the distortion factor is improved.

5. 发明专利

JPS62269507A VARIABLE GAIN AMPLIFIER 失效
公开(公告)号：JPS62269507A
公开(公告)日：1987-11-24
申请号：JP11274386
申请日：1986-05-19
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： TSUKAHARA TSUNEO , AKAZAWA YUKIO
IPC分类号： H03F3/30 , H03F3/20 , H03F3/34 , H03F3/345 , H03G3/12
摘要： PURPOSE:To contrive broad band and lower power consumption by connecting one stage of a CMOS inverter and another CMOS inverter having feedback to the input/output through a variable resistor in cascade so as to constitute a variable gain amplifier, thereby eliminating the need for a level shift circuit and a capacitor. CONSTITUTION:A unit amplifier 3 consists of complementary inverters 1, 2 connected in cascade and a variable resistor Ef1 and the resistor Rf1 is connected between the input and output of the inverter 2 to form a negative feedback path. Thus, the gain is made variable by the resistor Rf1, and since the input impedance of the amplifier is capacitive due to the input capacitance, no gain effect is caused in case of multi-stage connection because the amplifier of the next stage gives effect on the band via its input capacitance. Thus, the direct coupling malti-stage is attained without a capacitance and a level shift circuit and the amplifier amplifying a signal from a DC componet is realized with less band deterioration and low power consumption.

6. 发明专利

JPS60183806A AMPLIFIER CIRCUIT 失效
公开(公告)号：JPS60183806A
公开(公告)日：1985-09-19
申请号：JP3879784
申请日：1984-03-02
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： ISHIHARA NOBORU , AKAZAWA YUKIO , OBARA MAMORU
IPC分类号： H03F3/45
摘要： PURPOSE:To obtain two AC output characteristics of positive and negative phases with good symmetry over a broad band by zeroing a series feedback resistor connected to an emitter of transistor (TR) of differential pairs, adding a resistor in series with a collector of a constant current TR or operating the collector and emitter at opposite junction. CONSTITUTION:A base of the 1st TR is used as an AC signal input and a DC bias setting terminal and each base of the 2nd and 3rd TRs is used as a DC bias setting terminal respectively, in such a series feedback differential amplifier, a total bias current of TRs Q1-7 and Q2-7 is set by adjusting a DC voltage source circuit V3 in caption 12, values of the DC voltage source circuit V1 and a DC voltage source circuit V2 in caption 13 are set so that the currents of the TRs Q1, Q2 are identical, and two balance signals with broad band of positive and opposite phase are obtained from terminals 14, 15 by applying an AC signal to an input terminal 18 being the base of the TRQ1.

7. 发明专利

JPS60111517A IMPEDANCE CONVERTING CIRCUIT 失效
公开(公告)号：JPS60111517A
公开(公告)日：1985-06-18
申请号：JP22027983
申请日：1983-11-21
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： AKAZAWA YUKIO , ISHIHARA NOBORU , OBARA MAMORU
IPC分类号： H03H11/28 , H03H11/40
摘要： PURPOSE:To attain fcree direct-couling with an amplifier stage and an electronic circuit realized in an IC by coupling an emitter follower circuit and a serial/ parallel feedback circuit to set freely the output impedance and increase the input impedance. CONSTITUTION:An output of a stage 10 consisting of a transistor (TR) Q1 and resistors R1-R4 and having an ordinary gain is fed to an input terminal 11 of an impedance converting circuit 9. The circuit 9 consists of an emitter follower level shift circuit and a serial/parallel feedback amplifier circuit and the output of the emitter follower level shift circuit is connected to the input of the serial parallel feedback circuit. Furthermore, the emitter follower level shift circuit is constituted by connecting a TRQ2, a level shift circuit 8 and resistors R5, R6 as shown in the figure and the serial parallel amplifier circuit is constituted by connecting a TRQ3 and resistors R7-R9 as shown in Fig.

8. 发明专利

JPS60111512A LIMITER AMPLIFIER CIRCUIT 失效
公开(公告)号：JPS60111512A
公开(公告)日：1985-06-18
申请号：JP22027883
申请日：1983-11-21
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： AKAZAWA YUKIO , WAKIMOTO TSUTOMU , OBARA MAMORU
IPC分类号： H03G11/02 , H03G11/00
摘要： PURPOSE:To attain ease of monolithic circuit integration by inserting a high resistance between a feedback path and a gate of a transistor (TR) and connecting an input signal terminal to the gate so as to attain a suitable characteristic and improve the gain and input impedance thereby decreasing the coupling capacitance at multi-stage constitution. CONSTITUTION:A resistor R4 of several kohms is inserted between a connecting point of resistors R2, R3 and a gate of an MESFET5 and the gate is used as an input terminal 1. Thus, even if an input potential is a low potential, the input voltage component superimposed on an output voltage via the resistor R2 is limited by the resistor R4 and even if the value of the resistor R2 is decreased to set a limiter output level smaller, an excellent characteristic is obtained. In selecting the resistor R4 as a value larger than the resistors R2, R3, the input impedance is nearly the value of the resistor R4, the coupling capacitance is decrease in case of multi-stage constitution and monolithic circuit integration is performed easily.

9. 发明专利

JPS6043910A MONOLITHIC VARIABLE PHASE SHIFTER 失效
公开(公告)号：JPS6043910A
公开(公告)日：1985-03-08
申请号：JP15159983
申请日：1983-08-22
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： KIKUCHI HIROYUKI , OBARA MAMORU , AKAZAWA YUKIO
IPC分类号： H03H7/20
摘要： PURPOSE:To attain full monolithic configuration through a semiconductor integrated circuit by utilizing a reverse bias characteristic of a diode made of a semiconductor PN junction so as to realize a capacitance of an RC variable phase shifter thereby conducting phase shift with high accuracy by means of a variable voltage. CONSTITUTION:A value of a reference voltage source of either the 1st reference voltage source 38 or the 3rd reference voltage source 44 and of either the 2nd reference voltage source 39 or the 4th reference voltage source 45 is controlled while keeping always diodes D1, D2 in the reverse bias state so as to make the capacitance value of the PN junction variable thereby adjusting the phase shift amount. In order that a DC component of an input signal gives no effect on the reverse bias characteristic of the diodes, the input signal is cut off in terms of DC by means of a capacitor C1. Further, the transfer of the signal to the diode D1 side is performed via a capacitor C2 and a DC bias is given to the diodes D1, D2 via the 1st and 3rd resistors R1 and R3.

10. 发明专利

JPS5810918A DIGITAL-TO-ANALOG CONVERTER 失效
公开(公告)号：JPS5810918A
公开(公告)日：1983-01-21
申请号：JP10813581
申请日：1981-07-13
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： MATSUTANI YASUYUKI , AKAZAWA YUKIO , IWATA ATSUSHI
IPC分类号： H03M1/10 , H03M1/00 , H03M1/68 , H03K13/02
摘要： PURPOSE:To realize the high speed of a titled converter and to decrease the scale of a storage circuit, by instantly determining a switching point from a digital signal of a part of an input code. CONSTITUTION:A control signal is supplied to a bus selector 6A from a sequencer B via a signal line 9C and the input terminal C is selected. Thus, an input code Din inputted from a terminal 1 is latched to a latch 8. Next, a bus selector 6B selects an input terminal B, drives an ROM5B and a readout output is transferred to an adder 4 and summed with the input code Din latched at the latch 8. A sequencer 7 discriminates whether the content of a digit corresponding to the most significant bit of an original DAC is 1 or 0 as the result of summing, and the obtained result is latched to the latch 8. This is respetitively done for the low-order biet number (m). When this processing is finished, the bus selector 6B selects an input terminals A, drives an ROM5A, and the readout result is summed to a code obtained with the said repetition.

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