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1. 发明专利

JP2013134792A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2013134792A
公开(公告)日：2013-07-08
申请号：JP2011284154
申请日：2011-12-26
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： HIRAISHI ATSUSHI , KANNO TOSHIO , NARUI SEIJI , TAKAI YASUHIRO
IPC分类号： G11C11/401 , G11C11/4076 , G11C11/4093
CPC分类号： G11C7/222 , G11C7/1057 , G11C7/1066
摘要： PROBLEM TO BE SOLVED: To perform an ODT operation properly even when input timing of a data signal and a data strobe signal is offset.SOLUTION: A semiconductor device comprises: data strobe terminals 17a and 17b; output drivers 218 and 219 respectively connected to data strobe terminals 17a and 17b; data terminals 16-0 to 16-7; output drivers 210 to 217 respectively connected to the data terminals 16-0 to 16-7; and a data control circuit 100 that, in response to ODT control command ODTcontA, causes the output drivers 218 and 219 and the output drivers 210 to 217 to function as termination resistors at a different timing from each other. According to the present invention, the value of the termination resistor does not change during reception of a data signal DQ even when a reception timing of the data signal DQ and that of a data strobe signal DQS are offset in write operation.
摘要翻译：要解决的问题：即使当数据信号和数据选通信号的输入定时被偏移时也能适当地执行ODT操作。解决方案：半导体器件包括：数据选通端子17a和17b; 分别连接到数据选通端子17a和17b的输出驱动器218和219; 数据终端16-0至16-7; 分别连接到数据端子16-0至16-7的输出驱动器210至217; 以及数据控制电路100，其响应于ODT控制命令ODTcontA使得输出驱动器218和219以及输出驱动器210至217在彼此不同的定时用作终端电阻器。根据本发明，即使数据信号DQ的接收定时和数据选通信号DQS的接收定时在写入操作中被偏移，终端电阻的值也不会在接收数据信号DQ期间改变。

2. 发明专利

JP2007243735A Dll circuit and semiconductor device comprising the same 审中-公开
标题翻译： DLL电路和包含其的半导体器件
公开(公告)号：JP2007243735A
公开(公告)日：2007-09-20
申请号：JP2006064935
申请日：2006-03-09
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： TAKAI YASUHIRO
IPC分类号： H03L7/081 , G11C11/407 , G11C11/4076 , H03K5/13 , H03K5/131
CPC分类号： H03L7/0814 , H03L7/107
摘要： PROBLEM TO BE SOLVED: To provide a DLL (Delay Locked Loop) circuit capable of preventing data from being erroneously latched affected by jitter when generating a signal synchronized with a reference clock signal.
SOLUTION: The DLL circuit comprises: a delay circuit 12 for outputting signals D1, D2 delaying a reference clock signal CLK according to control signals C1, C2; an interpolation circuit 13 for interpolating a phase difference between the signals D1, D2; an output circuit 14, 15 for outputting DQ/DQS signals with internal clock signals CLK0 as timing references; a dummy output circuit 16 which inputs the internal clock signal CLK0 and outputs a feedback clock signal RCLK of the same phase as that of the DQ/DQS signal; a phase comparator circuit 17 for comparing phases of the reference clock signal CLK and the feedback clock signal RCLK; and first and second delay control circuits 18, 19 each for controlling the increase/decrease of the control signal C1, C2 in a phase matching direction, wherein the signal D2 is controlled to enlarge a delay time only for one cycle of the reference clock signal CLK in comparison with the signal D1.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种DLL（延迟锁定环路）电路，其能够防止在产生与参考时钟信号同步的信号时受抖动影响的数据被错误锁存。解决方案：DLL电路包括：延迟电路12，用于输出根据控制信号C1，C2延迟参考时钟信号CLK的信号D1，D2; 内插电路13，用于内插信号D1，D2之间的相位差; 用于以内部时钟信号CLK0作为定时参考输出DQ / DQS信号的输出电路14,15; 输入内部时钟信号CLK0并输出与DQ / DQS信号相同相位的反馈时钟信号RCLK的虚拟输出电路16; 用于比较参考时钟信号CLK和反馈时钟信号RCLK的相位的相位比较器电路17; 以及用于控制相位匹配方向上的控制信号C1，C2的增减的第一和第二延迟控制电路18,19，其中控制信号D2以仅延长参考时钟信号的一个周期的延迟时间 CLK与信号D1相比较。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2007006517A Delay-locked loop device 有权
标题翻译：延迟锁定装置
公开(公告)号：JP2007006517A
公开(公告)日：2007-01-11
申请号：JP2006214056
申请日：2006-08-07
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： TAKAI YASUHIRO , KOBAYASHI KATSUTARO
IPC分类号： G06F1/10 , G11C11/407 , G11C11/4076 , H03K5/13
摘要： PROBLEM TO BE SOLVED: To provide a device for achieving jitter reduction and area reduction of a DLL. SOLUTION: A delay-locked loop device comprises: a first delay circuit line including a plurality of stages of delay units 101-110; a second delay circuit line including a plurality of stages of delay units 111-121; and a plurality of transfer circuits 131-141 provided in accordance with each stage of the first delay circuit line for controlling transfer of outputs from the stages of the first delay circuit line to corresponding stages of the second delay circuit line based on control signals that are input thereto, respectively. The delay units 101-110 on the stages of the first delay circuit line invert out input signals, a delay unit on each stage of the second delay circuit line includes a logic circuit which inputs an output of the transfer circuit corresponding to the delay unit and an output of a delay unit on the preceding stage of the delay unit and outputs an output signal to the following stage and by independently selecting propagation paths of rising and falling edges of an inputted signal, a duty ratio is made variable. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供用于实现DLL的抖动减小和面积减小的装置。解决方案：延迟锁定环路装置包括：包括多级延迟单元101-110的第一延迟电路线; 包括多级延迟单元111-121的第二延迟电路线; 以及根据第一延迟电路线的每一级设置的多个传送电路131-141，用于基于控制信号控制从第一延迟电路线的级到第二延迟电路线的相应级的输出的传送分别输入。第一延迟电路线的各级的延迟单元101-110反转输入信号，第二延迟电路线的每一级的延迟单元包括输入与延迟单元对应的传送电路的输出的逻辑电路，以及在延迟单元的前一级上的延迟单元的输出，并将输出信号输出到后级，并且通过独立地选择输入信号的上升沿和下降沿的传播路径，使占空比变化。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2009284266A Dll circuit 有权
标题翻译： DLL电路
公开(公告)号：JP2009284266A
公开(公告)日：2009-12-03
申请号：JP2008134775
申请日：2008-05-22
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： TAKAI YASUHIRO
IPC分类号： H03L7/081 , H03K5/135
CPC分类号： H03L7/0814 , H03K5/13 , H03K5/133 , H03K2005/00052 , H03L7/0818
摘要： PROBLEM TO BE SOLVED: To provide a DLL circuit for reducing the minimum operation cycle of an interpolation circuit, and raising the maximum operating frequency of DLL.
SOLUTION: A phase detection circuit 21 detects the difference of phase between a reference clock signal to be input and a clock signal to be output from a replica circuit 17 to be output to a delay control circuit 22. The delay control circuit 22 outputs a control signal for adjusting the phase of the reference clock signal on the basis of a signal with phase difference. Then, multiplexers 12, 13 select and output a signal with delay difference for two stages of inverters from a coarse adjustment delay circuit 10 on the basis of the control signal to be output from the delay control circuit 22, and a first fine adjustment delay circuit 14 outputs a signal with delay difference for one stage of inverter on the basis of the signal with delay difference for two stages input from a multiplexer. A second fine adjustment delay circuit 15 adjusts the phase of the clock signal on the basis of the signal with delay difference for one stage.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供用于减小内插电路的最小操作周期并提高DLL的最大工作频率的DLL电路。解决方案：相位检测电路21检测待输入的参考时钟信号与要从复制电路17输出的时钟信号之间的相位差，以输出到延迟控制电路22.延迟控制电路22 基于具有相位差的信号输出用于调整参考时钟信号的相位的控制信号。然后，多路复用器12,13基于从延迟控制电路22输出的控制信号，从粗调延迟电路10选择并输出两级反相器的具有延迟差的信号，以及第一微调延迟电路基于从多路复用器输入的两级具有延迟差的信号，输出一级逆变器的延迟差的信号。第二微调延迟电路15基于具有一级延迟差的信号来调整时钟信号的相位。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2009152658A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2009152658A
公开(公告)日：2009-07-09
申请号：JP2007326220
申请日：2007-12-18
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： IDE AKIRA , TAKAI YASUHIRO , SEKIGUCHI TOMONORI , TAKEMURA RIICHIRO , AKIYAMA SATORU , NAKATANI HIROAKI
IPC分类号： H03K19/0175 , G06F1/04 , G11C11/4076 , H01L21/8242 , H01L27/108 , H03K5/00 , H03K5/13 , H03K5/131
CPC分类号： G11C7/22 , G11C7/04 , G11C7/1048 , G11C7/12 , G11C7/20 , G11C7/222 , G11C11/4094 , H01L27/0207 , H01L27/108 , H01L27/10897 , H03K5/15066
摘要： PROBLEM TO BE SOLVED: To provide a timing control circuit exhibiting a small timing variation for variation of power supply voltage or temperature, and to provide a semiconductor device equipped with that circuit. SOLUTION: A semiconductor device includes a first clock generation circuit and a second clock generation circuit employing an input clock, and a timing generation circuit receiving a first clock signal, a second clock signal, an activation signal from a command decoder, and a select signal for selecting a delay time from a timing register and generating a timing corresponding to a time combining a time equal to m times first period and a time equal to n times second period defined by the select signal from activation of the activation signal, wherein m and n are predetermined and the timing register stores the values of m and n, and storing in the timing register is carried out in an initialization sequence at the time of a mode register set command. Under an operating state, a timing signal is output at a desired timing from the timing generation circuit based on the information stored in the timing register. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有小的定时变化以用于电源电压或温度变化的定时控制电路，并提供配备有该电路的半导体器件。解决方案：半导体器件包括采用输入时钟的第一时钟产生电路和第二时钟产生电路，以及从命令解码器接收第一时钟信号，第二时钟信号，激活信号的定时产生电路和选择信号，用于从定时寄存器中选择延迟时间，并产生与组合等于第一周期m倍的时间的时间相对应的时间和等于由激活信号激活的选择信号定义的第n个时间段的时间的定时，其中m和n是预定的，并且定时寄存器存储m和n的值，并且在模式寄存器设置命令时以初始化顺序执行在定时寄存器中的存储。在运行状态下，基于存储在定时寄存器中的信息，从定时发生电路以期望的定时输出定时信号。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2009021704A Duty detection circuit and dll circuit using the same, semiconductor memory device, and data processing system 有权
标题翻译：占空比检测电路和使用其的DLL电路，半导体存储器件和数据处理系统
公开(公告)号：JP2009021704A
公开(公告)日：2009-01-29
申请号：JP2007181358
申请日：2007-07-10
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： KUROKI KOJI , TAKAI YASUHIRO
IPC分类号： H03L7/085 , H03K5/05 , H03L7/081
CPC分类号： G11C11/4076 , G11C7/22 , G11C7/222 , H03L7/0814 , H03L7/087
摘要： PROBLEM TO BE SOLVED: To provide a duty detection circuit applicable to a multi-phase DLL circuit in which discharge speed and charging speed can be kept constant and a large potential difference appears on the detection line, and to provide a DLL circuit employing it. SOLUTION: The duty detection circuit comprising discharge transistors TR1 and TR2, charging transistors TR3 and TR4, detection lines LDUTYHB and LDUTYLB, and a comparison circuit COMP for detecting the potential difference of the detection lines is further provided with gate control circuits G11-G14 for controlling the discharge transistors TR1, TR2 and the charging transistors TR3, TR4 in response to an internal clock signal in an even cycle. The detection line is charged/discharged in response to the internal clock signal in the even cycle, the duty detection circuit is applicable to a multi-phase DLL circuit and the potential difference appearing on the detection line can be ensured sufficiently. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种适用于其中放电速度和充电速度可以保持恒定并且在检测线上出现大的电位差的多相DLL电路的占空比检测电路，并且提供DLL电路雇用它解决方案：包括放电晶体管TR1和TR2，充电晶体管TR3和TR4，检测线LDUTYHB和LDUTYLB的占空比检测电路和用于检测检测线的电位差的比较电路COMP还具有栅极控制电路G11 -G14，用于响应于偶数周期中的内部时钟信号来控制放电晶体管TR1，TR2和充电晶体管TR3，TR4。检测线在偶数周期内响应于内部时钟信号进行充电/放电，占空比检测电路可应用于多相DLL电路，并且可以充分确保出现在检测线上的电位差。版权所有（C）2009，JPO＆INPIT

7. 发明专利

JP2005116048A Anti-fuse programming circuit 审中-公开
标题翻译：抗保险丝编程电路
公开(公告)号：JP2005116048A
公开(公告)日：2005-04-28
申请号：JP2003348311
申请日：2003-10-07
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： TAKAI YASUHIRO
IPC分类号： G11C29/00 , G11C17/16 , G11C17/18 , H01L21/82
CPC分类号： G11C29/027 , G11C17/16 , G11C17/18
摘要： PROBLEM TO BE SOLVED: To stabilize an anti-fuse programming, and also to provide the anti-fuse programming circuit reduced in the number of elements thereof. SOLUTION: The anti-fuse programming circuit consists of a plurality of ant-fuses, a 1st transistor M1 for selecting an anti-fuse AF for programming from the plurality of anti-fuses, and a 2nd transistor M2. The circuit is characterized in that a selection signal SEL for selecting the anti-fuse AF is applied to the gate of the 1st transistor M1, the source is connected to a 1st power source VBB, the drain of the 2nd transistor M2 is connected to a 2nd power source VDD, the source is connected to the drain of the 1st transistor, the a programming voltage VPP is applied to one of the terminals of the anti-fuse AF, and the other terminal is connected to the drain of the 1st transistor M1. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了稳定反熔丝编程，并且还提供减少其元件数量的反熔丝编程电路。解决方案：反熔丝编程电路由多个反熔丝组成，第一晶体管M1用于选择用于从多个抗熔丝编程的反熔丝AF和第二晶体管M2。该电路的特征在于，用于选择反熔丝AF的选择信号SEL被施加到第一晶体管M1的栅极，源极连接到第一电源VBB，第二晶体管M2的漏极连接到第二电源VDD，源极连接到第一晶体管的漏极，编程电压VPP施加到反熔丝AF的一个端子，另一端连接到第一晶体管M1的漏极。版权所有（C）2005，JPO＆NCIPI

8. 发明专利

JP2009021706A Dll circuit and semiconductor memory device employing the same, and data processing system 审中-公开
标题翻译：使用其的DLL电路和半导体存储器件以及数据处理系统
公开(公告)号：JP2009021706A
公开(公告)日：2009-01-29
申请号：JP2007181360
申请日：2007-07-10
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： KUROKI KOJI , TAKAI YASUHIRO , FUJISAWA HIROKI
IPC分类号： H03L7/081 , G11C11/4076 , H03K5/13 , H03L7/087 , H03L7/10
CPC分类号： H03L7/087 , H03L7/0814 , H03L7/0818 , H03L7/10
摘要： PROBLEM TO BE SOLVED: To provide a DLL circuit for determining an amount of delay at high speed even if the number of bits of a count signal for adjusting FDL is increased.
SOLUTION: The DLL circuit comprises a delay line (CDL) 10 for delaying a clock signal at a relatively coarse adjustment pitch, a delay line (FDL) 20 for delaying a clock signal at a relatively fine adjustment pitch, and phase detection circuits 41 and 42 and counter control circuits 51 and 52 for controlling the delay of delay lines 10 and 20. The counter control circuits 51 and 52 control the delay line 10 by linear searching method and controls the delay line 20 by dichotomizing search method. Consequently, the amount of delay can be determined at high speed even if the number of bits of a count signal for adjusting the delay line 20 is increased.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：即使用于调整FDL的计数信号的位数增加，也提供用于确定高速延迟量的DLL电路。解决方案：DLL电路包括用于以较粗调整间距延迟时钟信号的延迟线（CDL）10，用于延迟相对精细调节间距的时钟信号的延迟线（FDL）20以及相位检测电路41和42以及用于控制延迟线10和20的延迟的计数器控制电路51和52.计数器控制电路51和52通过线性搜索方法控制延迟线10，并通过二分法搜索方法控制延迟线20。因此，即使用于调整延迟线20的计数信号的位数增加，也可以高速度地确定延迟量。版权所有（C）2009，JPO＆INPIT

9. 发明专利

JP2008227619A Phase comparison circuit 有权
标题翻译：相位比较电路
公开(公告)号：JP2008227619A
公开(公告)日：2008-09-25
申请号：JP2007059091
申请日：2007-03-08
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： TAKAI YASUHIRO
IPC分类号： H03L7/091 , G06F1/12
CPC分类号： H03D13/004
摘要： PROBLEM TO BE SOLVED: To provide a phase comparison circuit which has a short delay time and can reliably prevent a malfunction of a post-stage circuit even when a metastable occurs. SOLUTION: A D-F/F 21 reads an external clock signal CLK1 on the basis of a control clock signal RCLK. Inverters INVA1, INVB1 having difference threshold level inverts the output of an inverter 22 to output it. Inverters INVA2, INVB2 having hysteresis characteristics inverts the outputs of inverters INVA1, INVB1 to output it. When the outputs of the inverters INVA2, INVB2 are coincident, an EX-NOR circuit 30, a D-latch 31 and an AND gate 32 add the output of the delay circuit 33 to a D-FF23 and a delay circuit 34, and if not coincident, turn off the outputs. The D-F/F23 reads the output of the inverter 22 on the basis of a delay signal of the control clock signal RCLK to be supplied via the AND gate 32, and outputs the read output. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种相位比较电路，其具有短的延迟时间，并且即使在亚稳态发生时也可以可靠地防止后级电路的故障。解决方案：D-F / F21基于控制时钟信号RCLK读取外部时钟信号CLK1。具有差阈值电平的反相器INVA1，INVB1使逆变器22的输出反相输出。具有滞后特性的反相器INVA2，INVB2使反相器INVA1，INVB1的输出反相输出。当反相器INVA2，INVB2的输出一致时，EX-NOR电路30，D锁存器31和与门32将延迟电路33的输出加到D-FF23和延迟电路34上，如果不符合，关闭输出。 D-F / F23根据要通过“与”门32提供的控制时钟信号RCLK的延迟信号读取反相器22的输出，并输出读出的输出。版权所有（C）2008，JPO＆INPIT

10. 发明专利

JP2007188395A Clock signal generation circuit 审中-公开
标题翻译：时钟信号发生电路
公开(公告)号：JP2007188395A
公开(公告)日：2007-07-26
申请号：JP2006007271
申请日：2006-01-16
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： TAKAI YASUHIRO
IPC分类号： G06F1/06 , H03K5/15
CPC分类号： G11C7/22 , G11C7/222 , H03K3/0315 , H03K3/354
摘要： PROBLEM TO BE SOLVED: To provide a clock signal generation circuit which generates a high-speed 4 phase clock signal. SOLUTION: Logic inversion circuits 10a, 10b, 10c and 10d of the same constitution are respectively provided with a PMOS transistor MP1 (abbreviated to be only MP1, hereafter), NMOS transistors MN1 and MN2 (abbreviated to be only MN1 and MN2, hereafter). The gates of the MP1 and the MN1 are connected to an input terminal IN1, the gate of the MN2 is connected to an input terminal IN2, the drains of the MP1 and the MN1 are connected to an output terminal OUT, the source of the MN1 is connected to the drain of the MN2, and the source of the MP1 is connected to a controllable power source VC to ground the source of the MN2. The respective input terminals IN1 and IN2 of the logic inversion circuits 10a, 10b, 10c and 10d are connected to the respective output terminals OUT of the logic inversion circuits 10b/10c, 10c/10d, 10d/10a, and 10a/10b. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种产生高速4相时钟信号的时钟信号发生电路。解决方案：具有相同结构的逻辑反相电路10a，10b，10c和10d分别设置有PMOS晶体管MP1（以下简称为MP1），NMOS晶体管MN1和MN2（简称为MN1和MN2 ，以下）。 MP1和MN1的栅极连接到输入端子IN1，MN2的栅极连接到输入端子IN2，MP1和MN1的漏极连接到输出端子OUT，MN1的源极连接到MN2的漏极，MP1的源极连接到可控电源VC，以对MN2的源进行接地。逻辑反相电路10a，10b，10c和10d的各个输入端子IN1和IN2连接到逻辑反相电路10b / 10c，10c / 10d，10d / 10a和10a / 10b的各个输出端子OUT。版权所有（C）2007，JPO＆INPIT

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