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1. 发明专利

JP6394056B2 A/D変換装置、グレイコード生成装置、撮像素子、並びに、電子機器有权
公开(公告)号：JP6394056B2
公开(公告)日：2018-09-26
申请号：JP2014100185
申请日：2014-05-14
申请人：ソニー株式会社
发明人：武田祐一 , 鈴木篤史 , 佐伯貴範 , 高橋知宏
IPC分类号： H03M1/56 , H03K5/15 , H04N5/378
CPC分类号： H04N5/37455 , H03K5/135 , H03K23/005 , H03K2005/00052 , H03L7/08 , H03M1/12 , H03M1/123 , H03M1/56 , H04N5/378

2. 发明专利

JP2017523659A 容量性要素を使用して位相補間器の線形性を改善すること有权
公开(公告)号：JP2017523659A
公开(公告)日：2017-08-17
申请号：JP2016571711
申请日：2015-05-14
申请人：クゥアルコム・インコーポレイテッドQualcomm Incorporated , クゥアルコム・インコーポレイテッドQualcomm Incorporated
发明人：スン、リ , ジュ、ジ , コン、シャオファ
IPC分类号： H03L7/00 , H03K5/00
CPC分类号： H03K5/13 , H03K2005/00052 , H03K2005/00286 , H04L7/0025 , H04L7/02
摘要：電源電圧に結合された負荷抵抗器のペアと、負荷抵抗器のペアに結合された複数の分岐、各分岐は、ソースノードを形成するためにソース端子において接続されたトランジスタの差動ペアを含む、と、複数のテール電流源、各テール電流源は、ソースノードのうちの1つに結合される、と、複数の結合キャパシタ、各結合キャパシタは、複数の分岐のうちの2つの隣接する分岐中のソースノード間に結合される、とを含む、位相補間器。【選択図】図6

3. 发明专利

JP2015226163A 位相補間器审中-公开
标题翻译：相位插值器件
公开(公告)号：JP2015226163A
公开(公告)日：2015-12-14
申请号：JP2014109497
申请日：2014-05-27
申请人：富士通株式会社
发明人：坂井靖文 , 森俊彦
IPC分类号： G06F1/04 , H03H11/16 , H03H11/20
CPC分类号： H03K5/13 , G06F1/022 , H03K2005/00052 , H04L2027/0016 , H04L27/18 , H04L7/0025
摘要：【課題】位相線形性を劣化させることなく、信号を高周波数化することができる位相補間器を提供することを課題とする。【解決手段】位相補間器は、位相が異なる複数の余弦波又は正弦波の入力信号の位相を合成するミキサ(101)と、位相制御信号に応じたバイアス信号を前記ミキサに出力するバイアス生成器(102)とを有し、前記ミキサは、前記位相制御信号に応じた位相の信号を出力する。【選択図】図1
摘要翻译：要解决的问题：提供能够使信号频率更高而不降低相位线性的相位插值装置。解决方案：相位插值装置包括：混频器（101），用于组合多个余弦和正弦输入信号的相位有不同的阶段; 以及用于根据相位控制信号向混频器输出偏置信号的偏置发生器（102）。混频器根据相位控制信号输出相位信号。

5. 发明专利

JP2011097314A Multiphase clock generation circuit 有权
标题翻译：多相时钟发生电路
公开(公告)号：JP2011097314A
公开(公告)日：2011-05-12
申请号：JP2009248432
申请日：2009-10-29
申请人： Nec Corp , 日本電気株式会社
发明人： NEDACHI TAKAAKI
IPC分类号： H03K5/15
CPC分类号： H03L7/0814 , H03K5/13 , H03K2005/00052 , H03K2005/00058 , H03K2005/00208 , H03K2005/00286 , H03L7/0807 , H03L7/091
摘要： PROBLEM TO BE SOLVED: To resolve a problem that it is hard to use a phase interpolation circuit with high performance in wide band operational frequencies.
SOLUTION: A multiphase clock generation circuit 10 generates a multiphase clock having any phase from a plurality of reference clocks having different phases by using phase interpolation. A phase selecting circuit 12 is a variable slew rate circuit whose slew rate changes according to a control signal. Phase interpolation circuits 13-1, 13-2 subject two reference clocks having phases different in phase by 90° from each other that are inputted through the phase selecting circuit 12 to interpolation to generate an output clock having an intermediate phase.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：解决在宽带工作频率下难以使用具有高性能的相位插值电路的问题。解决方案：多相时钟产生电路10通过使用相位插值从具有不同相位的多个参考时钟产生具有任何相位的多相时钟。相位选择电路12是其转换速率根据控制信号而变化的可变转换速率电路。相位插值电路13-1,13-2将通过相位选择电路12输入的具有相位相差90°的两个参考时钟进行插值，以产生具有中间相位的输出时钟。版权所有（C）2011，JPO＆INPIT

6. 发明专利

JP2010074201A Synchronization detection circuit, pulse width modulation circuit using the same and synchronization detection method 审中-公开
标题翻译：同步检测电路，脉冲宽度调制电路及同步检测方法
公开(公告)号：JP2010074201A
公开(公告)日：2010-04-02
申请号：JP2008235840
申请日：2008-09-16
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： HEIKO YASUYUKI
IPC分类号： H03K5/00 , H03K5/15 , H03K7/08 , H03L7/06 , H03L7/08
CPC分类号： H03K7/08 , H03K5/135 , H03K2005/00052 , H03L7/0998 , H03L7/18
摘要： PROBLEM TO BE SOLVED: To provide a synchronization detection circuit in which the number of parts is reduced, high detection accuracy is ensured and deterioration in processing speed is prevented. SOLUTION: The synchronization detection circuit 2 has: a polyphase clock generating circuit 11 for generating polyphase clock signals of a plurality of phases having phases different from each other, on the basis of a reference clock signal by a phase locked-loop circuit 15; and a synchronous clock specifying circuit 12 for specifying the clock signal that synchronizes, with the synchronous signal from among the polyphase clock signals. The polyphase clock generating circuit 11 generates a high-speed polyphase clock signal, having a frequency obtained, by multiplying the reference clock signal and a low-speed polyphase clock signal, having a frequency obtained by dividing the high-speed polyphase clock signal, and the synchronous clock specifying circuit generates a synchronization position signal, indicating the synchronous position of the synchronous signal, on the basis of a result of comparison between the synchronization signal and the high-speed polyphase clock signal and a result of comparison between the synchronous signal and a representative clock signal selected from the low-speed polyphase clock signal. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供减少部件数量的同步检测电路，确保了高检测精度，并且防止了处理速度的劣化。解决方案：同步检测电路2具有：多相时钟生成电路11，用于基于由锁相环电路的基准时钟信号，生成具有彼此相位不同的多相的多相时钟信号 15; 以及用于指定与多相时钟信号中的同步信号同步的时钟信号的同步时钟指定电路12。多相时钟发生电路11产生高频多相时钟信号，该高速多相时钟信号具有通过乘以具有通过划分高速多相时钟信号而获得的频率的基准时钟信号和低速多相时钟信号而获得的频率，以及同步时钟指定电路根据同步信号和高速多相时钟信号的比较结果，生成表示同步信号的同步位置的同步位置信号，同步信号与从低速多相时钟信号中选择的代表时钟信号。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2009284266A Dll circuit 有权
标题翻译： DLL电路
公开(公告)号：JP2009284266A
公开(公告)日：2009-12-03
申请号：JP2008134775
申请日：2008-05-22
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： TAKAI YASUHIRO
IPC分类号： H03L7/081 , H03K5/135
CPC分类号： H03L7/0814 , H03K5/13 , H03K5/133 , H03K2005/00052 , H03L7/0818
摘要： PROBLEM TO BE SOLVED: To provide a DLL circuit for reducing the minimum operation cycle of an interpolation circuit, and raising the maximum operating frequency of DLL.
SOLUTION: A phase detection circuit 21 detects the difference of phase between a reference clock signal to be input and a clock signal to be output from a replica circuit 17 to be output to a delay control circuit 22. The delay control circuit 22 outputs a control signal for adjusting the phase of the reference clock signal on the basis of a signal with phase difference. Then, multiplexers 12, 13 select and output a signal with delay difference for two stages of inverters from a coarse adjustment delay circuit 10 on the basis of the control signal to be output from the delay control circuit 22, and a first fine adjustment delay circuit 14 outputs a signal with delay difference for one stage of inverter on the basis of the signal with delay difference for two stages input from a multiplexer. A second fine adjustment delay circuit 15 adjusts the phase of the clock signal on the basis of the signal with delay difference for one stage.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供用于减小内插电路的最小操作周期并提高DLL的最大工作频率的DLL电路。解决方案：相位检测电路21检测待输入的参考时钟信号与要从复制电路17输出的时钟信号之间的相位差，以输出到延迟控制电路22.延迟控制电路22 基于具有相位差的信号输出用于调整参考时钟信号的相位的控制信号。然后，多路复用器12,13基于从延迟控制电路22输出的控制信号，从粗调延迟电路10选择并输出两级反相器的具有延迟差的信号，以及第一微调延迟电路基于从多路复用器输入的两级具有延迟差的信号，输出一级逆变器的延迟差的信号。第二微调延迟电路15基于具有一级延迟差的信号来调整时钟信号的相位。版权所有（C）2010，JPO＆INPIT

8. 发明专利

JP2009239768A Semiconductor integrated circuit device and method for clock data recovery 审中-公开
标题翻译：半导体集成电路器件及时钟数据恢复方法
公开(公告)号：JP2009239768A
公开(公告)日：2009-10-15
申请号：JP2008085174
申请日：2008-03-28
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： UMAI SEIICHI , ISEZAKI TSUYOSHI
IPC分类号： H03L7/06 , H03K5/00 , H04L7/02
CPC分类号： H04L7/0337 , H03K5/156 , H03K2005/00052 , H03L7/07 , H03L7/0814 , H03L7/089 , H03L7/0998 , H04L7/0025
摘要： PROBLEM TO BE SOLVED: To provide a clock data recovery circuit of an interpolator type capable of corresponding to multi-rate data without increasing the bandwidth of an interpolator circuit. SOLUTION: A clock generated by an interpolator circuit is divided to generate a recovery clock. A pointer that controls the phase of the clock generated by the interpolator circuit uses the clock before division, and the other circuits are operated by using the recovery clock after division. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供能够对应于多速率数据而不增加内插器电路的带宽的内插器类型的时钟数据恢复电路。解决方案：由内插器电路产生的时钟被分割以产生恢复时钟。控制由内插电路产生的时钟的相位的指针在分频之前使用时钟，并且分频后通过使用恢复时钟来操作其它电路。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP2008182667A Dll circuit and method of controlling the same 有权
标题翻译： DLL电路及其控制方法
公开(公告)号：JP2008182667A
公开(公告)日：2008-08-07
申请号：JP2007224004
申请日：2007-08-30
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： SHIN DONG SUK , LEE HYUN-WOO , YUN WON JOO
IPC分类号： H03L7/081 , G11C11/4076 , H03K5/04 , H03L7/087
CPC分类号： H03K5/133 , H03K5/1565 , H03K2005/00052 , H03K2005/00065 , H03L7/0814 , H03L7/087
摘要： PROBLEM TO BE SOLVED: To provide a DLL circuit outputting a clock having an improved duty ratio quality, and a method of controlling the same. SOLUTION: A DLL circuit of the present invention includes: a duty ratio detection unit that detects a duty ratio of a rising clock and a duty ratio of a falling clock, thereby outputting a duty ratio detection signal; a correction control unit that generates a correction control signal in response to the duty ratio detection signal; and a duty ratio correction unit that corrects a duty ratio of an internal clock in response to the correction control signal, thereby outputting a reference clock. COPYRIGHT: (C)2008,JPO&INPIT

10. 发明专利

JP2006217544A Oscillator 审中-公开
标题翻译：振荡器
公开(公告)号：JP2006217544A
公开(公告)日：2006-08-17
申请号：JP2005030998
申请日：2005-02-07
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： UCHIYAMA HISAYOSHI , WAKAI FUTOSHI
IPC分类号： H03L7/099 , H03K3/0231 , H03K3/282
CPC分类号： H03L7/0998 , H03K3/0322 , H03K5/13 , H03K2005/00052 , H03L7/0995 , H03L7/10
摘要： PROBLEM TO BE SOLVED: To realize a stable oscillation operation by avoiding a deterioration and a deadlock state in phase noise characteristics in an oscillator using a current controlled type oscillation circuit. SOLUTION: Resistors Q1 and Q3 are inserted into respective current paths of a differential pair of a differential amplifier circuit constituting an oscillation frequency control circuit to relax inclination in linear areas of output currents Ia and Ib of the differential pair. Reference voltage to be applied to the base of one transistor of the differential pair is set low to thereby shift the linear area to a low voltage side, preventing the occurrence of a saturation area at the low voltage side. Further, when converting a comparison result in phase between an output signal of the current controlled oscillation circuit and the reference signal into oscillation frequency control voltage, upper limit voltage closer to an output of a regulator is limited in place of a positive voltage power supply Vcc common to the circuit to thereby prevent the voltage from moving to a saturation area that is an upper side of the linear area. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过避免使用电流控制型振荡电路的振荡器的相位噪声特性的劣化和死锁状态来实现稳定的振荡操作。解决方案：电阻器Q1和Q3被插入构成振荡频率控制电路的差分放大器电路的差分对的相应电流路径中，以松弛差分对的输出电流Ia和Ib的线性区域中的倾斜。要施加到差分对的一个晶体管的基极的参考电压被设置为低，从而将线性区域移动到低电压侧，防止在低压侧出现饱和区域。此外，当将电流控制振荡电路的输出信号与参考信号之间的相位比较结果转换为振荡频率控制电压时，将接近调节器的输出的上限电压代替正电压电源Vcc 从而防止电压移动到作为线性区域的上侧的饱和区域。版权所有（C）2006，JPO＆NCIPI

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