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1. 发明专利

JP2009152658A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2009152658A
公开(公告)日：2009-07-09
申请号：JP2007326220
申请日：2007-12-18
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： IDE AKIRA , TAKAI YASUHIRO , SEKIGUCHI TOMONORI , TAKEMURA RIICHIRO , AKIYAMA SATORU , NAKATANI HIROAKI
IPC分类号： H03K19/0175 , G06F1/04 , G11C11/4076 , H01L21/8242 , H01L27/108 , H03K5/00 , H03K5/13 , H03K5/131
CPC分类号： G11C7/22 , G11C7/04 , G11C7/1048 , G11C7/12 , G11C7/20 , G11C7/222 , G11C11/4094 , H01L27/0207 , H01L27/108 , H01L27/10897 , H03K5/15066
摘要： PROBLEM TO BE SOLVED: To provide a timing control circuit exhibiting a small timing variation for variation of power supply voltage or temperature, and to provide a semiconductor device equipped with that circuit. SOLUTION: A semiconductor device includes a first clock generation circuit and a second clock generation circuit employing an input clock, and a timing generation circuit receiving a first clock signal, a second clock signal, an activation signal from a command decoder, and a select signal for selecting a delay time from a timing register and generating a timing corresponding to a time combining a time equal to m times first period and a time equal to n times second period defined by the select signal from activation of the activation signal, wherein m and n are predetermined and the timing register stores the values of m and n, and storing in the timing register is carried out in an initialization sequence at the time of a mode register set command. Under an operating state, a timing signal is output at a desired timing from the timing generation circuit based on the information stored in the timing register. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有小的定时变化以用于电源电压或温度变化的定时控制电路，并提供配备有该电路的半导体器件。解决方案：半导体器件包括采用输入时钟的第一时钟产生电路和第二时钟产生电路，以及从命令解码器接收第一时钟信号，第二时钟信号，激活信号的定时产生电路和选择信号，用于从定时寄存器中选择延迟时间，并产生与组合等于第一周期m倍的时间的时间相对应的时间和等于由激活信号激活的选择信号定义的第n个时间段的时间的定时，其中m和n是预定的，并且定时寄存器存储m和n的值，并且在模式寄存器设置命令时以初始化顺序执行在定时寄存器中的存储。在运行状态下，基于存储在定时寄存器中的信息，从定时发生电路以期望的定时输出定时信号。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2011175719A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2011175719A
公开(公告)日：2011-09-08
申请号：JP2010041091
申请日：2010-02-25
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： TAKAYAMA SHINICHI , KAJITANI KAZUHIKO , KOTABE AKIRA , AKIYAMA SATORU , SEKIGUCHI TOMONORI
IPC分类号： G11C11/407 , G11C11/4096
CPC分类号： G11C29/02 , G11C11/4091 , G11C11/4097 , G11C29/04 , G11C2207/002 , G11C2207/005
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device, capable of reducing the number of column selection lines for sense amplifier selection, and capable of sufficiently securing a power wiring layout area, while maintaining high-speed operation with a simple circuit structure. SOLUTION: The semiconductor device includes: bit lines (GBLL) connected to memory cells; sense amplifiers (SA) which are amplifiers connected to respective bit lines; local input/output lines (LIOT); input/output ports (IOP) which are local column switches; column selection lines (YS0); and global column switches (Q20, Q21). Because the sense amplifier (SA) is selectable by the column selection line (YS0) and two sense amplifier selection lines (ZEB, ZEB), it is possible to reduce the number of column selection lines (YS0) and sufficiently secure the power wiring layout area, while maintaining high-speed column selection with a small circuit scale. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：提供能够减少用于读出放大器选择的列选择线的数量并且能够充分确保电力布线布局区域的半导体器件，同时以简单的电路结构保持高速运行。解决方案：半导体器件包括：连接到存储器单元的位线（GBLL）; 感测放大器（SA），其是连接到相应位线的放大器; 本地输入/输出线（LIOT）; 作为本地列开关的输入/输出端口（IOP）; 列选择线（YS0）; 和全局列开关（Q20，Q21）。由于读出放大器（SA）可以通过列选择线（YS0）和两个读出放大器选择线（ZEB，ZEB）来选择，所以可以减少列选择线数（YS0）并充分确保电源布线布局区域，同时保持高速列选择与小电路规模。版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2008186547A Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：JP2008186547A
公开(公告)日：2008-08-14
申请号：JP2007020986
申请日：2007-01-31
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： NAKATANI HIROAKI , TAKEMURA RIICHIRO , AKIYAMA SATORU , SEKIGUCHI TOMONORI , NAKAMURA MASAYUKI , MIYATAKE SHINICHI
IPC分类号： G11C11/4091
CPC分类号： G11C11/4091 , G11C7/08 , G11C2207/005
摘要： PROBLEM TO BE SOLVED: To provide technology to control a shared MOS transistor gate voltage that can improve the sensing speed and quickly read data by preventing data inversion due to noise and reducing the bit line capacity when used for the low voltage. SOLUTION: The sensing speed is increased via a gate voltage control circuit of the shared MOS transistor connecting a sense amplifier and a memory cell array by considering the noise at sensing, lowering the shared MOS transistor gate voltage (SHR) in two steps and reducing the amplified bit line capacity. Thus, the column selection signal is quickly started, and the data read time is shortened. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供技术来控制共享的MOS晶体管栅极电压，其可以通过防止由于噪声导致的数据反转并且当用于低电压时降低位线容量来提高感测速度并快速读取数据。解决方案：通过考虑传感噪声连接读出放大器和存储单元阵列的共享MOS晶体管的栅极电压控制电路提高感测速度，分两步降低共享MOS晶体管栅极电压（SHR）并降低放大的位线容量。因此，列选择信号快速启动，数据读取时间缩短。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2008028055A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008028055A
公开(公告)日：2008-02-07
申请号：JP2006197602
申请日：2006-07-20
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： AKIYAMA SATORU , TSUCHIYA RYUTA , SEKIGUCHI TOMONORI , TAKEMURA RIICHIRO , NAKAMURA MASAYUKI , YAMAZAKI YASUSHI , SHIRATAKE SHIGERU
IPC分类号： H01L21/8242 , H01L21/3205 , H01L23/52 , H01L27/108
CPC分类号： H01L27/10894 , G11C7/18 , G11C11/404 , G11C11/4097 , H01L27/10876 , H01L27/10891 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a DRAM capable of realizing reduced power consumption, high-speed operation, and high reliability. SOLUTION: The gate electrode 7 of the memory cell transistor of the DRAM is formed of an n-type polycrystalline silicon film 7n and a W film 8 laminated thereon. Part of the polycrystalline silicon film 7n is embedded within the groove 13 formed in the silicon substrate 1 to increase the effective channel length of the memory cell transistor. The other part of the polycrystalline silicon film 7n is projected above the groove 13 and the top face thereof is located above the surface of the silicon substrate 1 (p-type well 3), so that the distances are ensured between the W film 8 and the source, and between the W film 8 and the drain (n-type semiconductor regions 9a, 9b). COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供能够实现降低功耗，高速运行和高可靠性的DRAM。解决方案：DRAM的存储单元晶体管的栅极7由层叠在其上的n型多晶硅膜7n和W膜8形成。多晶硅膜7n的一部分嵌入到形成在硅衬底1中的槽13内，以增加存储单元晶体管的有效沟道长度。多晶硅膜7n的另一部分突出在槽13的上方，其顶面位于硅衬底1（p型阱3）的表面上方，从而确保W膜8与源极，以及W膜8和漏极（n型半导体区域9a，9b）之间。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2007179681A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2007179681A
公开(公告)日：2007-07-12
申请号：JP2005378490
申请日：2005-12-28
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： HANZAWA SATORU , SEKIGUCHI TOMONORI , TAKEMURA RIICHIRO , AKIYAMA SATORU , KAJITANI KAZUHIKO
IPC分类号： G11C11/4096 , G11C11/407
CPC分类号： G11C7/1027 , G11C7/1012 , G11C7/1048 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1072 , G11C7/1078 , G11C7/1096 , G11C7/12 , G11C7/22 , G11C11/4076 , G11C11/4091 , G11C11/4093 , G11C11/4094 , G11C11/4096 , G11C29/028 , G11C2207/002
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which includes a semiconductor memory such as a DRAM, and achieves the expansion of an operation margin or reduction of power consumption. SOLUTION: Such a columnar circuit is provided for instance that a signal read out to a local input/output line LIO from a sense amplifier array SAA is amplified by sub-amplifiers and transferred to a main input/output line MIO. On each sub-amplifier, a current control circuit IC is prepared of which currents of two kinds can be set in accordance with e.g. read starting signals RD1, 2. The RD1, 2 are formed at timing corresponded to the number of cycles of burst read-out operation by the control of a timing control circuit. The current of the current control circuit IC is set to be large by the RD1 in the burst read-out operation cycle of a time immediately after the activation of a bank, and the current of the current control circuit IC is set to be small by the RD2 in the succeeding read-out operation. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种包括诸如DRAM的半导体存储器的半导体器件，并且实现了操作裕度的扩大或功耗的降低。解决方案：提供这种柱状电路，例如从读出放大器阵列SAA读出到本地输入/输出线LIO的信号由子放大器放大并被传送到主输入/输出线MIO。在每个子放大器上，准备电流控制电路IC，其中根据例如可以设置两种电流。读取起始信号RD1,2。RD1,2在与定时控制电路的控制的脉冲串读出操作的周期数相对应的定时形成。电流控制电路IC的电流通过在激活组之后的时间的脉冲串读出操作周期中的RD1被设置为较大，并且电流控制电路IC的电流被设置为小 RD2在后续的读出操作中。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2007042176A Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：JP2007042176A
公开(公告)日：2007-02-15
申请号：JP2005223012
申请日：2005-08-01
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： SEKIGUCHI TOMONORI , TAKEMURA RIICHIRO , AKIYAMA SATORU , HANZAWA SATORU , KAJITANI KAZUHIKO
IPC分类号： G11C29/42 , G11C11/401 , G11C29/04
CPC分类号： G06F11/1044 , G11C2029/0409
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device having a wide operating margin at the operation to make it finer, while suppressing an area penalty.
SOLUTION: An error code correcting system consisting of 64 bits data bit and 9 bits check bit with respect to a memory array ARY such as a DRAM is introduced, for instance, and an error correction code circuit ECC according to the above arrangement is disposed adjacent to a sense amplifier column SAA. In addition to a regular memory array consisting of such memory array ARY, a redundant memory array similarly furnished with the SAA and the adjacent ECC is provided in a chip to relieve a defect developed at the manufacture. In the ECC, error is corrected at an activate command, and the check bit is stored at a precharge command.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体存储装置，其在操作时具有较宽的操作裕度，以使其更细，同时抑制区域损失。解决方案：例如，引入了相对于诸如DRAM的存储器阵列ARY由64位数据位和9位校验位组成的错误代码校正系统，以及根据上述布置的纠错码电路ECC 被布置在与感测放大器列SAA相邻的位置。除了由这种存储器阵列ARY组成的常规存储器阵列之外，在芯片中提供类似于SAA和相邻ECC的冗余存储器阵列，以减轻在制造过程中产生的缺陷。在ECC中，在激活命令下修正错误，校验位存储在预充电命令中。版权所有（C）2007，JPO＆INPIT

7. 发明专利

JP2006172683A Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：JP2006172683A
公开(公告)日：2006-06-29
申请号：JP2005172077
申请日：2005-06-13
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： SEKIGUCHI TOMONORI , AKIYAMA SATORU , TAKEMURA RIICHIRO , HANZAWA SATORU , KAJITANI KAZUHIKO
IPC分类号： G11C11/404 , G11C11/401 , G11C11/409 , H01L21/8242 , H01L27/108
CPC分类号： G11C11/4094 , G11C7/12 , G11C7/18 , G11C11/4074 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/10882
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device especially useful for miniaturizing DRAM. SOLUTION: A write command is input from the outside, the voltages of bit lines BLT and BLB are constituted of VDL and VSS, voltages are written in the storage node SN of a capacitor via a memory cell transistor according to the threshold values (LVT: low threshold voltage, MVT: middle threshold voltage, and HVT: high threshold voltage) of the memory cell transistor. Then, a plate line PL connected to the plate side of the capacitor is driven from a voltage VPL to a voltage VPH. When the voltage of the storage node SN is increased by coupling, the bit line BLT is reduced from the voltage VDL to the voltage VDP, the voltages excessively written in the storage SN are reduced according to the sizes of the threshold voltages of the memory cell transistor, and a variance in voltages of the storage node SN caused by the variance of the threshold voltages is reduced. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供对DRAM的小型化特别有用的半导体存储装置。解决方案：从外部输入写入命令，位线BLT和BLB的电压由VDL和VSS构成，电压根据阈值经由存储单元晶体管写入电容器的存储节点SN中（LVT：低阈值电压，MVT：中间阈值电压以及HVT：高阈值电压）。然后，将连接到电容器的板侧的板线PL从电压VPL驱动到电压VPH。当存储节点SN的电压通过耦合增加时，位线BLT从电压VDL减小到电压VDP，过度写入存储SN的电压根据存储单元的阈值电压的大小而减小晶体管，并且由阈值电压的变化引起的存储节点SN的电压变化减小。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2011118998A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2011118998A
公开(公告)日：2011-06-16
申请号：JP2009277059
申请日：2009-12-04
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： SATO TAKENORI , KAJITANI KAZUHIKO , YANAGAWA YOSHIMITSU , SEKIGUCHI TOMONORI , KOTABE AKIRA , AKIYAMA SATORU
IPC分类号： G11C11/4097 , H01L21/8242 , H01L27/108
CPC分类号： G11C5/06 , G11C7/08 , G11C11/4091 , G11C11/4097 , H01L27/10876 , H01L27/10885
摘要： PROBLEM TO BE SOLVED: To improve a semiconductor device having a hierarchically bit line structure. SOLUTION: Two memory cells MC(a) and MC(b) to be accessed at the same time are sensed in a time division manner using two sensing amplifiers SA0 and SA0A, and restored at the same time. No switch is required in the middle of global bit lines GBLT0 and GBLB0, and no problem occurs in time-division restoration. Further, as the sensing amplifier SA0 and the sensing amplifier SA0A have the same parasitic CR model, high sensitivity can be ensured. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：改进具有分层位线结构的半导体器件。解决方案：使用两个感测放大器SA0和SA0A以时分方式感测要同时访问的两个存储单元MC（a）和MC（b），并同时恢复。在全局位线GBLT0和GBLB0的中间不需要开关，时分恢复没有问题。此外，由于感测放大器SA0和感测放大器SA0A具有相同的寄生CR模型，因此可以确保高灵敏度。版权所有（C）2011，JPO＆INPIT

9. 发明专利

JP2009064526A Timing control circuit and semiconductor storage device 有权
标题翻译：时序控制电路和半导体存储器件
公开(公告)号：JP2009064526A
公开(公告)日：2009-03-26
申请号：JP2007233001
申请日：2007-09-07
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： IDE AKIRA , TAKAI YASUHIRO , SEKIGUCHI TOMONORI , TAKEMURA RIICHIRO , AKIYAMA SATORU , NAKATANI HIROAKI
IPC分类号： G11C11/4076 , G11C11/407 , H03K5/135
CPC分类号： H03K5/15033
摘要： PROBLEM TO BE SOLVED: To provide a timing control circuit of less delay variation to a change of a process, an operating environment and the like. SOLUTION: A first clock CKa with a cycle T1, and a second clock group CKb of an L phase with a cycle T2 are input, in which L is an integer. When m, n are integers, a fine tuning timing signal FT is generated, wherein a delay amount from a rising edge of the first clock becomes td=m×T1+n×(T2/L). A coarse tuning delay circuit (CD) counts the rising edge of the first clock CKa after an activation signal (AC) is activated, and generates a coarse tuning timing signal CT, in which a delay amount from the first clock is m×T1. After an activation signal (ACT) is activated among the second clock group of the L phase, a fine tuning delay circuit (FD) detects the second clock which has a rising edge immediately after the rising edge of the first clock, and generates a fine tuning timing signal (FT), wherein a delay amount from the coarse tuning timing signal (CT) becomes almost n×(T2/L). COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供对于过程，操作环境等的改变具有较小延迟变化的定时控制电路。
解决方案：输入具有周期T1的第一时钟CKa和具有周期T2的L相的第二时钟组CKb，其中L是整数。当m，n是整数时，产生微调定时信号FT，其中从第一时钟的上升沿开始的延迟量为td = m×T1 + n×（T2 / L）。粗调谐延迟电路（CD）在激活信号（AC）激活之后对第一时钟CKa的上升沿进行计数，并产生一个粗调谐定时信号CT，其中第一时钟的延迟量为m×T1。在L相的第二时钟组中的激活信号（ACT）激活之后，微调延迟电路（FD）检测紧接在第一时钟的上升沿之后具有上升沿的第二时钟，并且产生罚款调谐定时信号（FT），其中来自粗调时序信号（CT）的延迟量变得几乎为n×（T2 / L）。版权所有（C）2009，JPO＆INPIT

10. 发明专利

JP2008251070A Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：JP2008251070A
公开(公告)日：2008-10-16
申请号：JP2007088693
申请日：2007-03-29
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： TAKEMURA RIICHIRO , SEKIGUCHI TOMONORI , AKIYAMA SATORU , NAKATANI HIROAKI , NAKAMURA MASAYUKI
IPC分类号： G11C11/4076 , G06F1/06 , G11C11/401 , G11C11/407 , H03K5/13
CPC分类号： G11C7/04 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C2207/2272
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which generates a proper inner timing signal according to manufacturing variation, operating voltage variation, and temperature change so as to provide a stable performance in a designated latency and external clock frequency.
SOLUTION: The semiconductor device has: a first delay circuit block which generates a timing signal for a circuit block for working in a column cycle time determined by an external input command cycle; and a second delay circuit block whose total delay is adjusted to a difference between the column cycle time and the access time determined by the external clock and latency. Regarding the delay circuit blocks, the delay of each delay circuit is properly adjusted according to the column latency and operating frequency, and also adjusted according to the variations of process and operating voltage and changes of the operating temperature as well.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供根据制造变化，工作电压变化和温度变化产生适当内部定时信号的半导体器件，以便在指定的等待时间和外部时钟频率下提供稳定的性能。解决方案：半导体器件具有：第一延迟电路块，其产生用于在由外部输入命令周期确定的列周期时间内工作的电路块的定时信号; 以及第二延迟电路块，其总延迟被调整为列周期时间与由外部时钟和等待时间确定的访问时间之间的差。关于延迟电路块，根据列延迟和工作频率适当地调整每个延迟电路的延迟，并且还根据工艺和工作电压的变化以及工作温度的变化进行调整。版权所有（C）2009，JPO＆INPIT

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