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1. 发明专利

JP2010152968A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2010152968A
公开(公告)日：2010-07-08
申请号：JP2008329252
申请日：2008-12-25
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： KUROKI KOJI
IPC分类号： G11C11/4076
CPC分类号： G11C11/4076 , G11C11/4094
摘要： PROBLEM TO BE SOLVED: To reduce power consumption in a semiconductor memory device having an automatic precharging function.
SOLUTION: The semiconductor memory device includes: clock generation circuits 70 and 80 for generating internal clocks ICLKW and ICLKWA, respectively; a latency counter for counting latency in synchronization with the internal clock ICLK; and a recovery counter for counting a write recovery period in synchronization with the internal clock ICLKWA. The lock generation circuit 80 activates the internal clock ICLKWA when automatic precharging is designated, and non-activates the internal clock ICLKWA when automatic precharging is not designated. Thus, the recovery counter 60 performs no counting operation when the automatic precharging function is not used, thereby preventing useless power consumption.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了降低具有自动预充电功能的半导体存储器件的功耗。解决方案：半导体存储器件包括：分别产生内部时钟ICLKW和ICLKWA的时钟产生电路70和80; 用于与内部时钟ICLK同步计数等待时间的延迟计数器; 以及用于与内部时钟ICLKWA同步地计数写恢复期的恢复计数器。当指定自动预充电时，锁产生电路80激活内部时钟ICLKWA，并且在未指定自动预充电时不激活内部时钟ICLKWA。因此，当不使用自动预充电功能时，恢复计数器60不执行计数操作，从而防止无用的功耗。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2009278528A Dll circuit, and semiconductor device 审中-公开
标题翻译： DLL电路和半导体器件
公开(公告)号：JP2009278528A
公开(公告)日：2009-11-26
申请号：JP2008129638
申请日：2008-05-16
申请人： Elpida Memory Inc , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立超エル・エス・アイ・システムズ
发明人： KUROKI KOJI , TAKISHITA TAKAHARU
IPC分类号： H03K5/04 , G06F1/06 , G11C11/4076 , H03K5/19 , H03L7/081
CPC分类号： H03L7/0814
摘要： PROBLEM TO BE SOLVED: To shorten a DLL clock cycle in lock control and to improve operational stability of a DLL circuit by preventing a delay amount from being updated, on the basis of a result of erroneous determination in phase detection, when a DLL clock disappears. SOLUTION: The DLL circuit includes: a delay control circuit 13 which outputs a delay signal for controlling a delay amount of a clock signal to be input; a delay circuit 12 which adds the delay amount based on the delay signal to the clock signal and outputs it as a DLL clock; and a DLL clock detection circuit 31 for detecting presence/absence of a clocking operation of the DLL clock signal. When the clocking operation of the DLL clock is not detected, the DLL clock detection circuit 31 then stops updating control of the delay amount due to the delay control circuit 13. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了缩短锁定控制中的DLL时钟周期，并且通过基于相位检测中的错误确定的结果，通过防止延迟量被更新来提高DLL电路的操作稳定性，当 DLL时钟消失。解决方案：DLL电路包括：延迟控制电路13，其输出用于控制要输入的时钟信号的延迟量的延迟信号; 延迟电路12，其将基于延迟信号的延迟量与时钟信号相加，并将其作为DLL时钟输出; 以及用于检测DLL时钟信号的时钟运算的存在/不存在的DLL时钟检测电路31。当未检测到DLL时钟的时钟操作时，DLL时钟检测电路31随后停止更新由延迟控制电路13引起的延迟量的控制。（C）2010，JPO＆INPIT

3. 发明专利

JP2009021704A Duty detection circuit and dll circuit using the same, semiconductor memory device, and data processing system 有权
标题翻译：占空比检测电路和使用其的DLL电路，半导体存储器件和数据处理系统
公开(公告)号：JP2009021704A
公开(公告)日：2009-01-29
申请号：JP2007181358
申请日：2007-07-10
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： KUROKI KOJI , TAKAI YASUHIRO
IPC分类号： H03L7/085 , H03K5/05 , H03L7/081
CPC分类号： G11C11/4076 , G11C7/22 , G11C7/222 , H03L7/0814 , H03L7/087
摘要： PROBLEM TO BE SOLVED: To provide a duty detection circuit applicable to a multi-phase DLL circuit in which discharge speed and charging speed can be kept constant and a large potential difference appears on the detection line, and to provide a DLL circuit employing it. SOLUTION: The duty detection circuit comprising discharge transistors TR1 and TR2, charging transistors TR3 and TR4, detection lines LDUTYHB and LDUTYLB, and a comparison circuit COMP for detecting the potential difference of the detection lines is further provided with gate control circuits G11-G14 for controlling the discharge transistors TR1, TR2 and the charging transistors TR3, TR4 in response to an internal clock signal in an even cycle. The detection line is charged/discharged in response to the internal clock signal in the even cycle, the duty detection circuit is applicable to a multi-phase DLL circuit and the potential difference appearing on the detection line can be ensured sufficiently. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种适用于其中放电速度和充电速度可以保持恒定并且在检测线上出现大的电位差的多相DLL电路的占空比检测电路，并且提供DLL电路雇用它解决方案：包括放电晶体管TR1和TR2，充电晶体管TR3和TR4，检测线LDUTYHB和LDUTYLB的占空比检测电路和用于检测检测线的电位差的比较电路COMP还具有栅极控制电路G11 -G14，用于响应于偶数周期中的内部时钟信号来控制放电晶体管TR1，TR2和充电晶体管TR3，TR4。检测线在偶数周期内响应于内部时钟信号进行充电/放电，占空比检测电路可应用于多相DLL电路，并且可以充分确保出现在检测线上的电位差。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2007115351A Synchronous semiconductor storage device 有权
标题翻译：同步半导体存储器件
公开(公告)号：JP2007115351A
公开(公告)日：2007-05-10
申请号：JP2005306418
申请日：2005-10-20
申请人： Elpida Memory Inc , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立超エル・エス・アイ・システムズ
发明人： KUBONAI SHUICHI , FUJISAWA HIROKI , KUROKI KOJI
IPC分类号： G11C11/407
CPC分类号： G11C11/4076 , G11C7/22 , G11C7/222
摘要： PROBLEM TO BE SOLVED: To provide a synchronous semiconductor storage device capable of counting a variety of latency while securing an operational margin upon using a fast external clock by suppressing the increase of consumption current.
SOLUTION: The device uses positive-phase/reverse-phase clocks PCLK0 and PCLK1 which are obtained by two-dividing an external clock and whose phases are different from each other by 180°, and comprises a first counter circuit comprising a shift register SR0 and selectors 31 and 32 operating at the positive-phase clock PCLK0 and a second counter circuit comprising a shift register SR1 and selectors 33 and 34 operating at the reverse-phase clock PCLK1. In setting an even-number latency, a signal path via only one of the counter circuit is constituted. In setting an odd-number latency, a signal path transiting between the two counter circuits is constituted. Thus, the variety of latency can be counted regardless of whether to set even or odd-number latency, so that the consumption current can be reduced and the margin of operation timing can be expanded.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种同步半导体存储装置，其能够通过抑制消耗电流的增加而在使用快速外部时钟的同时确保操作余量的同时计数各种等待时间。解决方案：器件使用通过将外部时钟进行二分割并且其相位彼此相差180°而获得的正相/反相时钟PCLK0和PCLK1，并且包括第一计数器电路，包括移位寄存器SR0和以正相位PCLK0工作的选择器31和32以及包括在反相时钟PCLK1上工作的移位寄存器SR1和选择器33和34的第二计数器电路。在设定偶数等待时间时，构成仅通过计数器电路之一的信号路径。在设置奇数等待时间时，构成在两个计数器电路之间转移的信号路径。因此，无论是否设置偶数或奇数等待时间，都可以计数各种等待时间，从而可以减少消耗电流并且可以扩大运行时间限制。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2011061620A Semiconductor device and level shift circuit 有权
标题翻译：半导体器件和电平移位电路
公开(公告)号：JP2011061620A
公开(公告)日：2011-03-24
申请号：JP2009210891
申请日：2009-09-11
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： DONO CHIAKI , KUROKI KOJI
IPC分类号： H03K19/0185
CPC分类号： H03K3/356182
摘要： PROBLEM TO BE SOLVED: To reduce layout area while preventing deterioration in duty of an output signal after level conversion and GCD mode trouble.
SOLUTION: A level shift circuit 100 is equipped with: a pair of P-channel transistors P1, P2 having sources connected to a power supply line VDDL and also connected in a flip-flop fashion; a pair of N-channel transistors N1, N2 provided between the transistors P1, P2 and the power supply line VSSL and inputting complementary input signals at respective gates; and a current supply circuit 11 provided between the power supply line VDDL and drains of the transistors N1, N2. The current supply circuit 11 is equipped with: N-channel transistors N3, N4 having sources connected to drains of the first transistors N1, N2; and P-channel transistors P3, P4 as current limiting elements each having one end connected to the power supply line VDDL and the other end connected to a drain of the transistor N3 or N4.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：减少布局面积，同时防止电平转换和GCD模式故障后输出信号的占空比降低。电平移位电路100配备有一对P沟道晶体管P1，P2，其源极连接到电源线VDDL并且以触发器方式连接; 设置在晶体管P1，P2和电源线VSSL之间的一对N沟道晶体管N1，N2，并在各个栅极输入互补输入信号; 以及设置在电源线VDDL和晶体管N1，N2的漏极之间的电流供给电路11。电流供应电路11配备有：具有连接到第一晶体管N1，N2的漏极的源极的N沟道晶体管N3，N4; 和P沟道晶体管P3，P4作为电流限制元件，每个限流元件的一端连接到电源线VDDL，另一端连接到晶体管N3或N4的漏极。版权所有（C）2011，JPO＆INPIT

6. 发明专利

JP2012049838A Semiconductor device and method of adjusting characteristics of the same 审中-公开
标题翻译：半导体器件及其调整特性的方法
公开(公告)号：JP2012049838A
公开(公告)日：2012-03-08
申请号：JP2010190271
申请日：2010-08-27
申请人： Elpida Memory Inc , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立超エル・エス・アイ・システムズ
发明人： KUROKI KOJI , NAKAJIMA DAIKI , TAKISHITA RYUJI
IPC分类号： H03K19/0175
CPC分类号： H03K19/0005 , H03K19/017545 , H03K19/017581 , H04L25/0278
摘要： PROBLEM TO BE SOLVED: To suppress the number of clocks required to adjust the impedance of an output buffer.SOLUTION: A pull-up replica buffer is connected between a calibration terminal and power supply wiring, and its impedance is controlled by a DRZQP signal supplied from a counter. A pull-down replica buffer is connected between ground wiring and a connection node A, and its impedance is controlled by a DRZQN signal supplied from the counter. More specifically, the DRZQP signal and the DRZQN signal indicate count values, and the impedance of the replica buffers is increased or decreased stepwise in proportion to the count values. The count values are updated according to a binary search method.
摘要翻译：要解决的问题：抑制调整输出缓冲器阻抗所需的时钟数。
解决方案：上拉复制缓冲器连接在校准端子和电源接线之间，其阻抗由计数器提供的DRZQP信号控制。接地布线和连接节点A之间连接一个下拉复制缓冲器，其阻抗由计数器提供的DRZQN信号控制。更具体地，DRZQP信号和DRZQN信号指示计数值，并且复制缓冲器的阻抗与计数值成比例地逐步增加或减小。根据二进制搜索方式更新计数值。版权所有（C）2012，JPO＆INPIT

7. 发明专利

JP2012049237A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2012049237A
公开(公告)日：2012-03-08
申请号：JP2010188311
申请日：2010-08-25
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： KUROKI KOJI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10897 , H01L23/5223 , H01L23/5225 , H01L23/5286 , H01L27/10894 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which a capacitative insulation film forming a compensation capacitative element is not broken.SOLUTION: The semiconductor device comprises a first power supply terminal 29 to which a first voltage is supplied, a second power supply terminal 23 to which a second voltage is supplied, a plurality of compensation capacitative elements 4 respectively having a capacitative insulation film 42 and a first and a second electrodes formed sandwiching the capacitative insulation film 42 and disposed in series between the first and the second power supply terminals 29, 23, first capacity connection wiring formed on a first wiring layer connecting an odd-numbered compensation capacitative elements 4 with an subsequent even-numbered compensation capacitative elements 4, second capacity connection wiring formed on a second wiring layer connecting the even-numbered compensation capacitative elements 4 with another subsequent odd-numbered compensation capacitative elements 4, and shield wiring 5 provided next to one of the first and the second capacity connection wiring for supplying substantially fixed voltage.
摘要翻译：要解决的问题：提供一种形成补偿电容元件的电容绝缘膜不被破坏的半导体器件。解决方案：半导体器件包括供给第一电压的第一电源端子29，提供第二电压的第二电源端子23，分别具有电容绝缘膜的多个补偿电容元件4 42和形成在第一和第二电源端子29,23之间串联布置的电容绝缘膜42的第一和第二电极，形成在连接奇数补偿电容元件的第一布线层上的第一电容连接布线 4，后续的偶数补偿电容元件4，形成在连接偶数补偿电容元件4与另一个后续奇数补偿电容元件4的第二布线层和旁边设置的屏蔽布线5的第二电容连接布线的第一和第二容量连接布线固定电压。版权所有（C）2012，JPO＆INPIT

8. 发明专利

JP2011050004A Semiconductor device and phase detection circuit 审中-公开
标题翻译：半导体器件和相位检测电路
公开(公告)号：JP2011050004A
公开(公告)日：2011-03-10
申请号：JP2009198794
申请日：2009-08-28
申请人： Elpida Memory Inc , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立超エル・エス・アイ・システムズ
发明人： KUROKI KOJI , TAKISHITA TAKAHARU
IPC分类号： H03K5/04 , H03K5/19 , H03K5/26 , H03L7/081 , H03L7/091
CPC分类号： H03L7/085 , G11C7/222 , H03K5/249 , H03L7/0814 , H03L7/0816
摘要： PROBLEM TO BE SOLVED: To provide a high accuracy phase detection circuit in which a wrong determination of phase detection is prevented. SOLUTION: Between a power supply line VSS1 and sense nodes LSAT, LSAB, sets of nMOS transistors (M1, M2, M3), (M4, M5, M6) are provided. An internal clock RCLK, an inverse signal of the internal clock RCLK due to an inverter INV1 and external clocks CK, /CK are input to a gate of each transistor, respectively. Between the power supply line VDD1 and the sense nodes LSAT, LSAB, sets of pMOS transistors (MP1, MP2, MP3), (MP4, MP5, MP6) are provided. An inverse signal of FCLK due to an inverter INV2, the internal clock RCLK and external clocks CL, /CK are input to a gate of each transistor, respectively. The sense nodes LSAT, LSAB are amplified by a differential amplifier AMP and latched by a latch circuit L1. PMOS transistors (MP11, MP12, MP13) precharge-equalize the LSAT, LSAB. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种高精度相位检测电路，其中防止了相位检测的错误确定。解决方案：在电源线VSS1和感测节点LSAT，LSAB之间提供nMOS晶体管（M1，M2，M3），（M4，M5，M6）组。内部时钟RCLK，由反相器INV1和外部时钟CK，/ CK引起的内部时钟RCLK的反相信号分别输入到每个晶体管的栅极。在电源线VDD1和感测节点LSAT，LSAB之间提供pMOS晶体管（MP1，MP2，MP3），（MP4，MP5，MP6）的集合。由于反相器INV2引起的FCLK的反相信号，内部时钟RCLK和外部时钟CL，/ CK分别输入到每个晶体管的栅极。感测节点LSAT，LSAB由差分放大器AMP放大并由锁存电路L1锁存。 PMOS晶体管（MP11，MP12，MP13）对LSAT，LSAB进行预充电。版权所有（C）2011，JPO＆INPIT

9. 发明专利

JP2011259062A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2011259062A
公开(公告)日：2011-12-22
申请号：JP2010129733
申请日：2010-06-07
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： BAN YOKO , KUROKI KOJI
IPC分类号： H03K19/0175 , H03K19/00 , H03K19/0185 , H03K19/0948
CPC分类号： G11C5/147 , Y10T307/696
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of maintaining an operation stability even when an external voltage changes.SOLUTION: An input signal determination part 116 is activated by power source potential supplied from a first current source 122. The input signal determination part 116 compares an input signal VIN and a reference potential Vref. The comparison result is inverted by an inverter INV1 to be an output signal V0. A power source sensor circuit 120 monitors a potential of a first power source line VDDI. When an external potential VDDI becomes lower than the reference potential VX, the power source sensor circuit 120 turns on a second current source 124. When the second current source 124 is turned on, an operation current is supplied to the determination part 126 from both the first current source 122 and the second current source 124.
摘要翻译：要解决的问题：提供即使当外部电压变化时也能够保持操作稳定性的半导体器件。
解决方案：输入信号确定部分116由从第一电流源122提供的电源电位激活。输入信号确定部分116比较输入信号VIN和参考电位Vref。比较结果由反相器INV1反转为输出信号V0。电源传感器电路120监视第一电源线VDDI的电位。当外部电位VDDI变得低于参考电位VX时，电源传感器电路120接通第二电流源124.当第二电流源124接通时，从确定部126向第一电流源122和第二电流源124.版权所有（C）2012，JPO＆INPIT

10. 发明专利

JP2009021706A Dll circuit and semiconductor memory device employing the same, and data processing system 审中-公开
标题翻译：使用其的DLL电路和半导体存储器件以及数据处理系统
公开(公告)号：JP2009021706A
公开(公告)日：2009-01-29
申请号：JP2007181360
申请日：2007-07-10
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： KUROKI KOJI , TAKAI YASUHIRO , FUJISAWA HIROKI
IPC分类号： H03L7/081 , G11C11/4076 , H03K5/13 , H03L7/087 , H03L7/10
CPC分类号： H03L7/087 , H03L7/0814 , H03L7/0818 , H03L7/10
摘要： PROBLEM TO BE SOLVED: To provide a DLL circuit for determining an amount of delay at high speed even if the number of bits of a count signal for adjusting FDL is increased.
SOLUTION: The DLL circuit comprises a delay line (CDL) 10 for delaying a clock signal at a relatively coarse adjustment pitch, a delay line (FDL) 20 for delaying a clock signal at a relatively fine adjustment pitch, and phase detection circuits 41 and 42 and counter control circuits 51 and 52 for controlling the delay of delay lines 10 and 20. The counter control circuits 51 and 52 control the delay line 10 by linear searching method and controls the delay line 20 by dichotomizing search method. Consequently, the amount of delay can be determined at high speed even if the number of bits of a count signal for adjusting the delay line 20 is increased.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：即使用于调整FDL的计数信号的位数增加，也提供用于确定高速延迟量的DLL电路。解决方案：DLL电路包括用于以较粗调整间距延迟时钟信号的延迟线（CDL）10，用于延迟相对精细调节间距的时钟信号的延迟线（FDL）20以及相位检测电路41和42以及用于控制延迟线10和20的延迟的计数器控制电路51和52.计数器控制电路51和52通过线性搜索方法控制延迟线10，并通过二分法搜索方法控制延迟线20。因此，即使用于调整延迟线20的计数信号的位数增加，也可以高速度地确定延迟量。版权所有（C）2009，JPO＆INPIT

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