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1. 发明专利

JP2005191434A Transistor, method for defining characteristics change model equation therefor and method for determining quality thereof 有权
标题翻译：晶体管，定义特征变化模型方程的方法及其质量测定方法
公开(公告)号：JP2005191434A
公开(公告)日：2005-07-14
申请号：JP2003433563
申请日：2003-12-26
申请人： Denso Corp , Toyota Central Res & Dev Lab Inc , 株式会社デンソー , 株式会社豊田中央研究所
发明人： WATANABE YUKIHIKO , YOSHIDA TOMOYUKI , TAI AKIRA , NAKAYAMA YOSHIAKI , NAKANO TAKASHI , MIZUNO SHOJI
IPC分类号： H01L21/66 , H01L21/331 , H01L29/68 , H01L29/732 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a method for determining the quality of a transistor in a short time.
SOLUTION: The transistor 12 has an n-type silicon layer 22 and a p-type silicon layer 20. The p-type silicon layer 20 is provided with a base electrode 12B and an emitter electrode 12E, and n-type electrode 22 with a corrector electrode 12C. The base electrode 12B and emitter electrode 12E are separated from the corrector electrode 12C via an interlayer insulating film 18. The transistor 12 also includes an electrode 16 which is arranged to cover a current flow passage in an area of the p-type silicon layer 20 that is at least between the base electrode 12B and the emitter electrode 12E via the interlayer insulating film 18. A voltage is applied to the electrode 16 to make electric charges move vigorously into the interlayer insulating film 18. This process makes it possible to determine the quality of the transistor more quicker than in a case where no voltage is applied to the electrode 16 in determining the quality of transistor.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于在短时间内确定晶体管的质量的方法。解决方案：晶体管12具有n型硅层22和p型硅层20.p型硅层20设置有基极12B和发射极12E，以及n型电极 22具有校正电极12C。基极电极12B和发射电极12E通过层间绝缘膜18与校正电极12C分离。晶体管12还包括布置成覆盖p型硅层20的区域中的电流流动通道的电极16 至少在基极电极12B和发射电极12E之间经由层间绝缘膜18。电压施加到电极16上，使电荷剧烈地移动到层间绝缘膜18中。这个过程使得可以确定晶体管的质量比在确定晶体管质量时没有电压施加到电极16的情况下更快。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2007251004A Characteristic prediction method and device for semiconductor device 有权
标题翻译：用于半导体器件的特性预测方法和器件
公开(公告)号：JP2007251004A
公开(公告)日：2007-09-27
申请号：JP2006074756
申请日：2006-03-17
申请人： Denso Corp , Toyota Central Res & Dev Lab Inc , 株式会社デンソー , 株式会社豊田中央研究所
发明人： NAKAJIMA KENJI , YOSHIDA TOMOYUKI , OTSUKI HIROSHI
IPC分类号： H01L21/66
摘要： PROBLEM TO BE SOLVED: To accurately predict the characteristics of a semiconductor device.
SOLUTION: The anisotropic etching of a high selection ratio is operated to a substrate or a predetermined layer, and cone-shaped etching residue formed with a crystal defect as a vertex is actualized (S12), and the etching residue is observed, and at least one of the density, shape and size of the crystal defect as the factor of the etching residue is evaluated (S16, S18), and the characteristics of the device are predicted based on at least one of the obtained density, shape and size of the crystal defect.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：准确地预测半导体器件的特性。解决方案：对基板或预定层进行高选择比的各向异性蚀刻，实现了以晶体缺陷为顶点形成的锥形蚀刻残留（S12），并观察蚀刻残留物，并且评估作为蚀刻残留因子的晶体缺陷的密度，形状和尺寸中的至少一个（S16，S18），并且基于获得的密度，形状和形状中的至少一个来预测器件的特性晶体缺陷的大小。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2007123469A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007123469A
公开(公告)日：2007-05-17
申请号：JP2005312389
申请日：2005-10-27
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： SUGIYAMA TAKAHIDE , YOSHIDA TOMOYUKI , HOTTA KOJI
IPC分类号： H01L29/739 , H01L21/265 , H01L21/336 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device comprising a semiconductor region containing impurities, wherein the technology suppresses a variation of a lattice constant in the semiconductor region.
SOLUTION: The semiconductor device sequentially comprises a first part 22 of a collector region 29 of an IGBT (Insulated Gate Bipolar Transistor), and contains boron at a high concentration; a second part 23 of the collector region 29 which contains boron and gallium at a high concentration in total; and a base region 24 containing phosphorus. In the second part 23, there mixedly exist boron of covalent radius smaller than that of silicon, and gallium of the covalent radius greater than that of silicon.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供包括含有杂质的半导体区域的半导体器件，其中该技术抑制半导体区域中的晶格常数的变化。解决方案：半导体器件依次包括IGBT（绝缘栅双极晶体管）的集电极区域29的第一部分22，并且含有高浓度的硼; 集电极区域29的第二部分23，其总共含有高浓度的硼和镓; 和含有磷的碱性区域24。在第二部分23中，混合存在共价半径小于硅的硼，并且共价半径的镓大于硅的镓。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2004063208A Ferroelectric blt film and its manufacturing process 审中-公开
公开(公告)号：JP2004063208A
公开(公告)日：2004-02-26
申请号：JP2002218666
申请日：2002-07-26
申请人： Toyota Central Res & Dev Lab Inc , 株式会社豊田中央研究所
发明人： KAGEYAMA YASUYUKI , ISHIHARA SHIHO , YOSHIDA TOMOYUKI , MITSUSHIMA KOICHI
IPC分类号： H01G4/12 , H01B3/12 , H01G4/33 , H01L21/822 , H01L21/8246 , H01L27/04 , H01L27/105
摘要： PROBLEM TO BE SOLVED: To provide a ferroelectric BLT film, in which crystal orientation to a direction of a film thickness is controlled, and its manufacturing process.
SOLUTION: For the ferroelectric BLT film, a peak intensity at an angle of diffraction of about 33.0° (a/b axis component) in an X-ray diffraction image in a direction of a film thickness is greater than a peak intensity at an angle of diffraction of about 30.0° (a component corresponding to a (117) plane). The ferroelectric film exhibiting such a/b axis orientation to the direction of the film thickness is obtained by repeating a cycle of applying a raw liquid containing each metal alkoxide of Bi, La and Ti to a substrate 1 and calcining it to form a calcined laminate 10' with calcined layers 12' having a thickness of 10 nm or smaller laminated on each other, and truly burning the calcined laminate 10' to form a burnt film 10. An additional burnt film 20 may be formed on the resultant burnt film 10.
COPYRIGHT: (C)2004,JPO

5. 发明专利

JP2007335432A Semiconductor device and its fabrication process 审中-公开
标题翻译：半导体器件及其制造工艺
公开(公告)号：JP2007335432A
公开(公告)日：2007-12-27
申请号：JP2006161938
申请日：2006-06-12
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： ISHIKO MASAYASU , YOSHIDA TOMOYUKI , KOIKE SHINJI , KIKUNI MASAHIRO , MIZUNO YOSHITO
IPC分类号： H01L21/28 , H01L21/336 , H01L29/41 , H01L29/739 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a vertical semiconductor device having a back electrode formed on the backside of a silicon substrate in which recesses (pits) are reduced in the backside of the silicon substrate.
SOLUTION: A collector electrode 20 has a first conductive layer 28, a second conductive layer 26, and a third conductive layer 24 formed sequentially from the backside of a silicon substrate 30. The first conductive layer 28 contains aluminum and silicon. The second conductive layer 26 contains titanium and has a mixture layer 26b further containing silicon or nitrogen at a part including an interface which touches at least the first conductive layer 28. The third conductive layer 24 contains nickel.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种垂直半导体器件，其具有形成在硅衬底的背面上的背电极，其中凹部（凹坑）在硅衬底的背面被减小。解决方案：集电极20具有从硅衬底30的后侧依次形成的第一导电层28，第二导电层26和第三导电层24.第一导电层28包含铝和硅。第二导电层26含有钛，并且在包含至少与第一导电层28接触的界面的部分处具有进一步含有硅或氮的混合层26b。第三导电层24含有镍。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2014144886A Method of producing czts compound semiconductor sintered compact 审中-公开
标题翻译：生产CZTS化合物半导体烧结的方法
公开(公告)号：JP2014144886A
公开(公告)日：2014-08-14
申请号：JP2013013992
申请日：2013-01-29
申请人： Toyota Motor Corp , トヨタ自動車株式会社 , Toyota Central R&D Labs Inc , 株式会社豊田中央研究所
发明人： TAKEDA YUICHIRO , SAKAI TAKENOBU , AWANO HIROMOTO , MATSUNAGA TOMOYA , MAEKAWA RYOSUKE , YOSHIDA TOMOYUKI , TAKEDA YASUHIKO , UMEHARA MITSUTARO
IPC分类号： C04B35/547 , C01G19/00 , H01L31/06
CPC分类号： Y02E10/50
摘要： PROBLEM TO BE SOLVED: To provide a method of producing a CZTS compound semiconductor sintered compact, capable of producing a dense CZTS compound semiconductor sintered compact at a firing temperature lower than that in a conventional method.SOLUTION: The method of producing a CZTS compound semiconductor sintered compact includes a step of firing a compact to be sintered containing Cu, Zn, Sn, and S under an environment where a sintering additive is present. The sintering additive contains zinc chloride.
摘要翻译：要解决的问题：提供一种生产CZTS化合物半导体烧结体的方法，其能够在低于常规方法的烧制温度下生产致密的CZTS化合物半导体烧结体。方法：制备CZTS化合物半导体的方法烧结体包括在存在烧结添加剂的环境下烧制含有Cu，Zn，Sn和S的烧结体的工序。烧结添加剂含有氯化锌。

7. 发明专利

JP2010278363A Crystal defect detecting method 审中-公开
标题翻译：水晶缺陷检测方法
公开(公告)号：JP2010278363A
公开(公告)日：2010-12-09
申请号：JP2009131520
申请日：2009-05-29
申请人： Toyota Central R&D Labs Inc , 株式会社豊田中央研究所
发明人： NAKAJIMA KENJI , YOSHIDA TOMOYUKI , OSHIO HIDETAKA , SHINOHARA SHO
IPC分类号： H01L21/66
摘要： PROBLEM TO BE SOLVED: To facilitate detecting crystal defects with high accuracy, even to a semiconductor material with a large area.
SOLUTION: Anisotropic etching of a high selection ratio is performed to crystal defects contained in the semiconductor material used as a crystal defect detection object by etching gas containing at least Cl
2 and O
2 . On an etching bottom face, there is exposed a semiconductor material protrusion formed using the crystal defects in the semiconductor material as a vertex, and the crystal defects are actualized, based on this protrusion for detection. To a Cl
2 flow rate 9 to an etching chamber, an O
2 flow rate is set up in a from about 0.8 to about 1. SF
6 may be contained. A flow rate of ≥0 and ≤0.4 is set up to the Cl
2 flow rate 9 or a flow rate of ≤1/2 is set up to the O
2 flow rate.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了便于高精度地检测晶体缺陷，即使是对具有大面积的半导体材料也是如此。解决方案：通过蚀刻至少含有Cl 2 和O 2的气体，对用作晶体缺陷检测对象的半导体材料中所含的晶体缺陷进行高选择比的各向异性蚀刻。在蚀刻底面上，以半导体材料中的晶体缺陷为顶点露出形成的半导体材料突起，并且基于该检测用突起而实现了晶体缺陷。对于蚀刻室的Cl 2 流速9，将O SB SB2流量设定为约0.8至约1. SF SB>。流量为≥0和≤0.4的流量设定为Cl 2 流量9或流量≤1/ 2设定为O 2 流量率。版权所有（C）2011，JPO＆INPIT

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