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1. 发明专利

JP2007335432A Semiconductor device and its fabrication process 审中-公开
标题翻译：半导体器件及其制造工艺
公开(公告)号：JP2007335432A
公开(公告)日：2007-12-27
申请号：JP2006161938
申请日：2006-06-12
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： ISHIKO MASAYASU , YOSHIDA TOMOYUKI , KOIKE SHINJI , KIKUNI MASAHIRO , MIZUNO YOSHITO
IPC分类号： H01L21/28 , H01L21/336 , H01L29/41 , H01L29/739 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a vertical semiconductor device having a back electrode formed on the backside of a silicon substrate in which recesses (pits) are reduced in the backside of the silicon substrate.
SOLUTION: A collector electrode 20 has a first conductive layer 28, a second conductive layer 26, and a third conductive layer 24 formed sequentially from the backside of a silicon substrate 30. The first conductive layer 28 contains aluminum and silicon. The second conductive layer 26 contains titanium and has a mixture layer 26b further containing silicon or nitrogen at a part including an interface which touches at least the first conductive layer 28. The third conductive layer 24 contains nickel.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种垂直半导体器件，其具有形成在硅衬底的背面上的背电极，其中凹部（凹坑）在硅衬底的背面被减小。解决方案：集电极20具有从硅衬底30的后侧依次形成的第一导电层28，第二导电层26和第三导电层24.第一导电层28包含铝和硅。第二导电层26含有钛，并且在包含至少与第一导电层28接触的界面的部分处具有进一步含有硅或氮的混合层26b。第三导电层24含有镍。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2007266133A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2007266133A
公开(公告)日：2007-10-11
申请号：JP2006086554
申请日：2006-03-27
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： KAWAJI SACHIKO , SUZUKI TAKASHI , ISHIKO MASAYASU , SAITO JUN , ONISHI TOYOKAZU
IPC分类号： H01L29/739 , H01L21/336 , H01L29/78
CPC分类号： H01L29/0623 , H01L29/0847 , H01L29/7395 , H01L29/7397
摘要： PROBLEM TO BE SOLVED: To provide a technique for excellently establishing compatibility between avoiding damage of a semiconductor device and reduction of an ON-voltage.
SOLUTION: The semiconductor device 11 is provided with an n
- -type drift region 25; an n
+ -type carrier accumulating region 26 contacting the drift region 25; a p
- -type body region 27 contacting the carrier accumulating region 26; an n
+ -type emitter region 29 contacting the body region 27; and a trench gate electrode 34 opposing the body region 27 positioned between the drift region 25 and the emitter region 29, and the carrier accumulating region 26 via a gate insulating film 32. The semiconductor device 11 is further provided with floating body regions 41. The floating body regions 41 are formed on a region including one part of the carrier accumulating region 26.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种在避免半导体器件损坏和降低导通电压之间良好建立兼容性的技术。解决方案：半导体器件11设置有n + SP> - 型漂移区25; 与漂移区域25接触的n + 型载流子蓄积区域26; 与载体积聚区域26接触的p - 型体区域27; 接触身体区域27的n 型发射体区域29; 以及沟槽栅极电极34，其与位于漂移区域25和发射极区域29之间的体区域27和载体积聚区域26相对，经由栅极绝缘膜32。半导体器件11还设置有浮动体区域41。浮动体区域41形成在包括载体积聚区域26的一部分的区域上。版权所有（C）2008，JPO＆INPIT

3. 发明专利

JP2007266132A Semiconductor device, manufacturing method thereof, and module provided therewith 审中-公开
标题翻译：半导体器件及其制造方法及其提供的模块
公开(公告)号：JP2007266132A
公开(公告)日：2007-10-11
申请号：JP2006086552
申请日：2006-03-27
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： KAWAJI SACHIKO , SUZUKI TAKASHI , ISHIKO MASAYASU , SAITO JUN , ONISHI TOYOKAZU , NISHIWAKI TAKESHI , SAITO HIROKAZU
IPC分类号： H01L23/34 , H01L23/36
CPC分类号： H01L24/32 , H01L2224/32225 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a vertical semiconductor device in which an ON-voltage or ON-resistance is low, and generated heat is dispersed. SOLUTION: The semiconductor device 70 is provided with a first layer 11, and a second layer 12 provided between the first layer 11 and a substrate 30. The first layer 11 has a rear surface electrode layer 71, a semiconductor layer 78 formed on the rear surface electrode layer 71, and a front surface electrode layer 88 formed on the semiconductor layer 78. A function structure configured by a plurality of kinds of semiconductor regions is incorporated into the semiconductor layer 78, and the function structure has a function of switching a current flowing between the front surface electrode layer 88 and the rear surface electrode layer 71 into a conduction state and a non-conduction state. The second layer 12 is joined to the rear surface electrode layer 71 of the first layer 11 without using solder, and at least a surface contacting the rear surface electrode layer 71 is configured of an insulator. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供一种导通电压或导通电阻低的分散的发热的立式半导体装置。解决方案：半导体器件70设置有第一层11和设置在第一层11和衬底30之间的第二层12.第一层11具有后表面电极层71，形成半导体层78 在后表面电极层71上形成的前表面电极层88和形成在半导体层78上的前表面电极层88.通过多个半导体区域构成的功能结构被结合到半导体层78中，并且功能结构具有将在前表面电极层88和背面电极层71之间流动的电流切换为导通状态和非导通状态。第二层12不使用焊料与第一层11的背面电极层71接合，至少与背面电极层71接触的面由绝缘体构成。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2006179815A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2006179815A
公开(公告)日：2006-07-06
申请号：JP2004373768
申请日：2004-12-24
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： KAWAJI SACHIKO , ISHIKO MASAYASU , SAITO JUN , HAMADA KIMIMORI
IPC分类号： H01L29/78 , H01L21/336 , H01L29/739
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that suppresses JFET phenomena and solves a tradeoff between break-down voltage and ON voltage.
SOLUTION: This semiconductor device contains a gate insulating film 42 formed continually from the surface of a p
- -type body region 34 separating the n
- -type semiconductor 12 and n
+ -type emitter region 32 to that of a semiconductor layer 12 positioned outside of a periphery 34a of the body region 34, and a planner gate electrode 44 opposed to the body region 34 interposing the insulating film 42 separating the semiconductor layer 12 and the emitter region 32. In addition, it contains an n
+ -type semiconductor region 52 formed along the periphery 34a of the body region 34 on the surface of the semiconductor layer 12 covered with the gate insulating film 42 and a p
+ -type semiconductor region 54 formed near the n
+ -type semiconductor region 52.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供抑制JFET现象的半导体器件，并且解决断开电压和导通电压之间的折中。解决方案：该半导体器件包含从分离n - 型半导体12的表面连续形成的栅极绝缘膜42和 n + 型发射极区域32与位于体区域34的周边34a外侧的半导体层12的栅极电极44相对，并且与插入绝缘膜42的主体区域34相对的整流栅极电极44 分离半导体层12和发射极区32.此外，其包含沿着半导体层12的表面的主体区域34的周边34a形成的n + SP +型半导体区域52 与栅极绝缘膜42和形成在n + SP型半导体区域52附近的ap + SP型半导体区域54.版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2005175062A Semiconductor device, and method for suppressing latch-up phenomenon 有权
标题翻译：半导体器件和用于抑制LATCH-UP PHENOMENON的方法
公开(公告)号：JP2005175062A
公开(公告)日：2005-06-30
申请号：JP2003410278
申请日：2003-12-09
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： KAWAJI SACHIKO , ISHIKO MASAYASU , HOTTA KOJI
IPC分类号： H01L29/78 , H01L29/739
摘要： PROBLEM TO BE SOLVED: To solve the problem of semiconductor device breakdown due to latch-up being generated upon the application of a high emitter/collector voltage.
SOLUTION: The semiconductor device comprises a p
- -type body region 28 formed on an n
- -type drift region 26, an n
+ -type emitter region 34 selectively formed in the body region 28, an emitter electrode E contacting with the emitter region 34, a trench gate electrode 32 penetrating through the body region 28, as far as the drift region 26 with the body region 28 separating the emitter region 34 and the drift region 26 from each other, and a p
+ -type semiconductor region 36 contacting with the emitter electrode E and penetrating through the body region 28 as far as the drift region 26. The p-type semiconductor region 36 is located outside the carrier transit region in the drift region 26 and is so positioned that the depletion layer, extending from the p-n junction interface between the p
+ -type semiconductor region 36 and the n
- -type drift region 26, infiltrates the carrier transit region upon increase in the emitter/collector voltage.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：解决由于在施加高发射极/集电极电压时产生的闩锁引起的半导体器件故障的问题。解决方案：半导体器件包括形成在n - / SP>型漂移区26上的ap - / SP>型体区28，n + SP 选择性地形成在体区28中的发射极区域34，与发射极区域34接触的发射极电极E，贯穿本体区域28的沟槽栅电极32，至少与体区28分离的漂移区域26 发射极区域34和漂移区域26，以及与发射极电极E接触并穿过体区28直到漂移区域26的p + SP +型半导体区域36。 p型半导体区域36位于漂移区域26内的载流子迁移区域的外侧，并且被定位成使得从pn结界面延伸到p 型半导体区域36和 n - / SP>型漂移区26在发射极/集电极电压增加时渗透载流子传输区。版权所有（C）2005，JPO＆NCIPI

6. 发明专利

JP2005079359A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005079359A
公开(公告)日：2005-03-24
申请号：JP2003308320
申请日：2003-09-01
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： KAWAJI SACHIKO , SUGIYAMA TAKAHIDE , SHOJI TOMOYUKI , ISHIKO MASAYASU , HOTTA KOJI
IPC分类号： H01L29/749 , H01L23/58 , H01L29/06 , H01L29/739 , H01L29/78
CPC分类号： H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To prevent thermal damage to a semiconductor device caused in a periphery region, and to obtain a high withstand voltage of the semiconductor device. SOLUTION: The semiconductor device has a central region M in which a semiconductor switch element group is formed, and a periphery region N in which a guard ring 38 group surrounding the central region M is formed. A body region 34 of the semiconductor switching element formed in an outermost periphery and a guard ring 38 formed in an innermost periphery are formed in an overlapped manner. Gate wiring 48 connected to a gate electrode 35 of the semiconductor switching element group is opposed to an overlapped region 39 between the body region 34 and the guard ring 38 through an insulating layer 46. The width of the overlapping region 39 is not less than 1/3 of the depth of either the body region 34 or the guard ring 38 whichever is deeper. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了防止在周边区域引起的对半导体器件的热损伤，并且获得半导体器件的高耐受电压。解决方案：半导体器件具有其中形成半导体开关元件组的中心区域M和形成有围绕中心区域M的保护环38组的外围区域N. 形成在最外周的半导体开关元件的主体区域34和形成在最内周的保护环38以重叠的方式形成。连接到半导体开关元件组的栅电极35的栅极布线48通过绝缘层46与体区域34和保护环38之间的重叠区域39相对。重叠区域39的宽度不小于1 / 3的身体区域34或保护环38的深度，以较深者为准。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2004140086A Trench gate semiconductor device 有权
公开(公告)号：JP2004140086A
公开(公告)日：2004-05-13
申请号：JP2002301909
申请日：2002-10-16
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： KAWAJI SACHIKO , ISHIKO MASAYASU , UEDA KENJI
IPC分类号： H01L29/06 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/0626
摘要： PROBLEM TO BE SOLVED: To provide a technique for restraining a dielectric breakdown from occurring in an insulating film covering a trench corner so as to raise the breakdown voltage of a trench gate semiconductor device.
SOLUTION: The trench gate semiconductor device is equipped with a semiconductor layer 20, a trench 23 formed in the semiconductor layer 20, and a trench gate electrode 24 buried in the trench 23 through the intermediary of an insulating film 30. The semiconductor layer 20 is equipped with a p-type outer region 46a formed outside of the inward end of the trench 23 and an n-type region 52 which is kept in contact with the p-type outer region 46a, has a conductivity type opposite to one possessed by the p-type outer region 46a, covers the upper corners 23a of the trench 23, and not the lower corners 23c of the trench 23.
COPYRIGHT: (C)2004,JPO

8. 发明专利

JP2007234972A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007234972A
公开(公告)日：2007-09-13
申请号：JP2006056568
申请日：2006-03-02
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： KAWAJI SACHIKO , SUZUKI TAKASHI , ISHIKO MASAYASU , SAITO JUN , NISHIWAKI TAKESHI , BABA HIROSUKE
IPC分类号： H01L29/78 , H01L21/225 , H01L21/336 , H01L29/739
摘要： PROBLEM TO BE SOLVED: To provide a technology of forming a region with a desired width and a desired depth by diffusing impurities from a trench groove of a semiconductor substrate.
SOLUTION: A manufacturing method of a semiconductor device disclosed herein includes: a step S2 of forming the trench groove S1 on the surface of the semiconductor substrate; steps S3, S4 of coating a wall face of the trench groove with SOG including a first conduction type impurity; and a step S5 of applying heat treatment to the semiconductor substrate to which the SOG is coated. The semiconductor region formed by impurity diffusion can be formed by a desired aspect ratio according to the manufacturing method of the semiconductor device.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供通过从半导体衬底的沟槽槽扩散杂质来形成具有期望宽度和期望深度的区域的技术。解决方案：本文公开的半导体器件的制造方法包括：在半导体衬底的表面上形成沟槽S1的步骤S2; 用包括第一导电类型杂质的SOG涂覆沟槽沟槽壁面的步骤S3，S4; 以及对涂覆有SOG的半导体衬底进行热处理的步骤S5。根据半导体器件的制造方法，可以通过期望的纵横比形成由杂质扩散形成的半导体区域。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2007173422A Semiconductor device, and method of manufacturing same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007173422A
公开(公告)日：2007-07-05
申请号：JP2005367417
申请日：2005-12-21
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： TAKI MASAHITO , KAWAKAMI MASAHIRO , HAYAKAWA KIYOHARU , ISHIKO MASAYASU
IPC分类号： H01L29/861 , H01L21/329 , H01L29/786
CPC分类号： H01L29/8611 , H01L21/266 , H01L29/0634 , H01L29/0878 , H01L29/1045 , H01L29/1083 , H01L29/1608 , H01L29/20 , H01L29/24 , H01L29/402 , H01L29/66128 , H01L29/66659 , H01L29/66681 , H01L29/7824 , H01L29/7835 , H01L29/78624
摘要： PROBLEM TO BE SOLVED: To improve a voltage sustained in the vertical direction in a lateral semiconductor device utilizing an SOI substrate. SOLUTION: A diode 10 comprises a semiconductor substrate 120, an embedded insulating film 130, the SOI substrate laminating a semiconductor layer 140, a rear surface semiconductor region 160 on the semiconductor layer 140, and an intermediate semiconductor region 153 and a front surface semiconductor region 154. The rear surface semiconductor region 160 includes an n-type impurity in higher concentration. The intermediate semiconductor region 153 includes an n-type impurity in lower concentration. The front surface semiconductor region 154 includes a p-type impurity. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：利用SOI衬底来提高在横向半导体器件中垂直方向上的电压。解决方案：二极管10包括半导体衬底120，嵌入绝缘膜130，层叠半导体层140的SOI衬底，半导体层140上的后表面半导体区域160以及中间半导体区域153和前端表面半导体区域154.背面半导体区域160包括较高浓度的n型杂质。中间半导体区域153包括较低浓度的n型杂质。前表面半导体区域154包括p型杂质。版权所有（C）2007，JPO＆INPIT

10. 发明专利

JP2007157799A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2007157799A
公开(公告)日：2007-06-21
申请号：JP2005347341
申请日：2005-11-30
申请人： Toyota Central Res & Dev Lab Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社豊田中央研究所
发明人： SUZUKI TAKASHI , KAWAJI SACHIKO , ISHIKO MASAYASU , SAITO JUN , SAITO HIROKAZU , HISANAGA YUKIHIRO
IPC分类号： H01L29/78 , H01L21/336 , H01L21/76 , H01L29/06 , H01L29/739
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device for improving an off withstand voltage by maintaining the charge balance of a peripheral region.
SOLUTION: The semiconductor device 1 has a center region M in which a semiconductor element is formed and the peripheral region N formed at the periphery of the center region. The device comprises a p
- -type body region 28 (impurity low-concentration semiconductor region); an insulating layer 42 that covers the surface side of the body region 28, and an electrically floating conductive member 70 while covering the surface of the insulating layer 42, at the peripheral region N.
COPYRIGHT: (C)2007,JPO&INPIT

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