专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2009057233A Method for evaluating compound semiconductor substrate, method for producing the same, and the compound semiconductor substrate 审中-公开
标题翻译：用于评价化合物半导体基板的方法，其制造方法和化合物半导体基板
公开(公告)号：JP2009057233A
公开(公告)日：2009-03-19
申请号：JP2007225054
申请日：2007-08-31
申请人： Covalent Materials Corp , National Institute For Materials Science , コバレントマテリアル株式会社 , 独立行政法人物質・材料研究機構
发明人： UCHIMARU TOMONORI , KANAI HIDEYUKI , KOMIYAMA JUN , SUZUKI SHUNICHI , NAKANISHI HIDEO , OSADA MINORU
IPC分类号： C30B29/38 , G01N21/65
摘要： PROBLEM TO BE SOLVED: To provide a method for evaluating a compound semiconductor substrate where, for producing a gallium nitride based compound semiconductor substrate of high quality, a fine crystal defect regarding a gallium nitride film can be easily confirmed at high precision using Raman spectroscopy, to provide a method for producing the same, and to provide the compound semiconductor substrate.
SOLUTION: Regarding the compound semiconductor substrate comprising a gallium nitride film, in the Raman spectroscopy spectra of scattered light obtained when the gallium nitride film is irradiated with monochromatic light with the excitation wavelength of 350 to 800 nm, by the appearance of the main peak in the region with the wave number of 565 to 570 cm
-1 and subpeaks caused by a crystal defect with the wave number of 100 to 700 cm
-1 , the presence of a crystal defect in the gallium nitride film is confirmed.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种用于评价化合物半导体衬底的方法，其中为了制造高质量的氮化镓基化合物半导体衬底，可以高精度地容易地确认关于氮化镓膜的微细晶体缺陷拉曼光谱法，以提供其制造方法，并提供化合物半导体衬底。解决方案：关于包含氮化镓膜的化合物半导体衬底，在氮化镓膜用激发波长为350至800nm的单色光照射时获得的散射光的拉曼光谱中，通过外观波数为565〜570cm -1的区域的主峰，由波数为100〜700cm -1的晶体缺陷引起的亚峰，证实在氮化镓膜中存在晶体缺陷。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2009238812A Inspecting method for compound semiconductor substrate 审中-公开
标题翻译：复合半导体衬底的检查方法
公开(公告)号：JP2009238812A
公开(公告)日：2009-10-15
申请号：JP2008079863
申请日：2008-03-26
申请人： Covalent Materials Corp , National Institute For Materials Science , コバレントマテリアル株式会社 , 独立行政法人物質・材料研究機構
发明人： UCHIMARU TOMONORI , KANAI HIDEYUKI , KOMIYAMA JUN , SUZUKI SHUNICHI , OSADA MINORU
IPC分类号： H01L21/66 , H01S5/00
摘要： PROBLEM TO BE SOLVED: To provide an inspecting method for a compound semiconductor substrate, in which quality is evaluated with high precision during inspection on a compound semiconductor substrate having a multilayer structure.
SOLUTION: The inspecting method for the compound semiconductor substrate 10 having a buffer layer and a GaN layer stacked in order on a semiconductor substrate includes a step (S1) of exposing a cross section in the stacking direction of the buffer layer and GaN layer, a step (S2) of irradiating the exposed cross section with laser light and evaluating stress at three points of the buffer layer and GaN layer in the section, and the interface between the buffer layer and GaN layer, and a step (S3) of plotting stress values of the stress at the three points on a coordinate surface showing stress values on its longitudinal axis and measurement positions on its lateral axis, and determining whether the compound semiconductor substrate 10 is good or not based on positions of the three plotted points on the coordinate surface.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种化合物半导体衬底的检查方法，其中在具有多层结构的化合物半导体衬底的检查期间以高精度评估质量。解决方案：具有在半导体衬底上依次堆叠的缓冲层和GaN层的化合物半导体衬底10的检查方法包括：在缓冲层的层叠方向上暴露横截面的步骤（S1）和GaN 层，步骤（S2），用激光照射暴露的横截面，并评估该截面中的缓冲层和GaN层的三个点以及缓冲层和GaN层之间的界面的应力，以及步骤（S3）绘制在坐标表面上的三个点上的应力的应力值，显示其纵轴上的应力值及其横轴上的测量位置，并且基于三个绘制点的位置来确定化合物半导体衬底10是否良好在坐标面上。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2009065025A Compound semiconductor substrate 审中-公开
标题翻译：化合物半导体基板
公开(公告)号：JP2009065025A
公开(公告)日：2009-03-26
申请号：JP2007232632
申请日：2007-09-07
申请人： Covalent Materials Corp , National Institute For Materials Science , コバレントマテリアル株式会社 , 独立行政法人物質・材料研究機構
发明人： KOMIYAMA JUN , SUZUKI SHUNICHI , NAKANISHI HIDEO , UCHIMARU TOMONORI , KANAI HIDEYUKI , OSADA MINORU
IPC分类号： H01L21/20 , C30B29/38 , H01L21/205 , H01L21/338 , H01L29/778 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a compound semiconductor substrate having a GaN active layer which is stress free as a whole by finding a simple method for measuring stress using Raman spectroscopy and controlling the stress in a buffer layer based on it.
SOLUTION: On a base substrate 1 composed of any one of hexagonal SiC with a thickness of 100-1,000 μm, single crystal Si or a cubic SiC layer formed on the single crystal Si, a buffer layer 2, and a GaN active layer 3 with a thickness of 0.5-5 μm are laminated sequentially. The buffer layer 2 is constituted of an Al
y Ga
1-y N single crystal layer (0.2≤y≤0.3)2b-1 with a thickness of 3-250 nm formed on an Al
x Ga
1-x N single crystal layer (0.5 x Ga
1-x N single crystal layer 2a-n with a thickness of 3-250 nm and an Al
z Ga
1-z N single crystal layer (0≤z
摘要翻译：要解决的问题：提供一种具有GaN活性层的化合物半导体衬底，其通过使用拉曼光谱法测量应力的简单方法并基于其控制缓冲层中的应力，从而整体上无应力。解决方案：在由任何一种厚度为100-1,000μm的六方晶系SiC构成的基底基板1上，单晶Si或形成在单晶Si上的立方SiC层，缓冲层2和GaN活性物质依次层叠厚度为0.5〜5μm的层3。缓冲层2由厚度为3-250nm的Al Y Ga 1-y / SB> N单晶层（0.2≤y≤0.3）2b-1构成形成在厚度为3-250nm的Al x Ga 1-x N N单晶层（0.5 x Ga 1-x N单晶层2a-n >0≤z<0.5）2c-n，厚度为3-250nm。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2009224722A Compound semiconductor board 审中-公开
标题翻译：化合物半导体板
公开(公告)号：JP2009224722A
公开(公告)日：2009-10-01
申请号：JP2008070249
申请日：2008-03-18
申请人： Covalent Materials Corp , コバレントマテリアル株式会社
发明人： ABE YOSHIHISA , KOMIYAMA JUN , SUZUKI SHUNICHI , OISHI KOJI , YOSHIDA AKIRA , NAKANISHI HIDEO
IPC分类号： H01L21/205 , H01L21/203 , H01L21/338 , H01L29/778 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a compound semiconductor substrate includes an intermediate layer which has electrical insulating properties and proper thermal conductivity.
SOLUTION: The compound semiconductor substrate includes: an Si single crystal substrate 100 having a crystal plane orientation of {111}; the intermediate layer 110, which is formed on the surface of the Si single-crystal substrate 100, and which is structured by alternatively laminating a plurality of first layers 110a, constituted of AlN and second layers 110b constituted of MgO, in order; and a nitride semiconductor single crystal layer 120, which is formed on the intermediate layer 110 and which is constituted of one among GaN (0001), AlN (0001) and InN (0001).
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种化合物半导体衬底，其包括具有电绝缘性和适当导热性的中间层。解决方案：化合物半导体衬底包括：晶体取向为ä111}的Si单晶衬底100; 形成在Si单晶衬底100的表面上的中间层110依次由层叠由AlN构成的多个第一层110a和由MgO构成的第二层110b构成。和形成在中间层110上并由GaN（0001），AlN（0001）和InN（0001）之一构成的氮化物半导体单晶层120。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2009218458A METHOD FOR MEASURING PHONON WAVENUMBER OF 3C-SiC LAYER ON Si SUBSTRATE 审中-公开
标题翻译：在Si衬底上测量3C-SiC层的on波的方法
公开(公告)号：JP2009218458A
公开(公告)日：2009-09-24
申请号：JP2008062090
申请日：2008-03-12
申请人： Covalent Materials Corp , コバレントマテリアル株式会社
发明人： SHIRAI HIROSHI , KOMIYAMA JUN
IPC分类号： H01L21/66 , G01N21/35 , G01N21/3563 , H01L21/205
摘要： PROBLEM TO BE SOLVED: To provide a method for measuring a phonon wavenumber of a 3C-SiC layer on a heavily doped Si substrate, which can simply measure a phonon spectrum of the 3C-SiC layer in non-destruction, high accuracy and high resolution in regard to a wafer wherein the 3C-SiC layer is formed on a heavily doped Si substrate by using an infrared reflection method. SOLUTION: An infrared reflection spectrum obtained when P polarized light is made obliquely incident on a reflector and an infrared reflection spectrum obtained when P polarized light is made incident on the surface of a wafer wherein a 3C-SiC layer is formed on a Si substrate at the same angle as the above incident angle are measured, and a reflection spectrum which is a ratio of the infrared reflection spectrum of the wafer wherein the 3C-SiC layer is formed on the Si substrate to the infrared reflection spectrum of the reflector is calculated to find out wavenumbers of a TO mode and an LO mode of a T 2 phonon with wavenumber vector k of ≈0. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于测量重掺杂Si衬底上的3C-SiC层的声子波数的方法，其可以简单地以非破坏性的方式测量3C-SiC层的声子谱，高精度并且通过使用红外反射法在重掺杂的Si衬底上形成3C-SiC层的晶片的高分辨率。解决方案：当P偏振光被倾斜地入射到反射器上时获得的红外反射光谱和当P偏振光入射到其上形成3C-SiC层的晶片的表面上获得的红外反射光谱测量与上述入射角成相同角度的Si衬底，反射光谱，其中在Si衬底上形成3C-SiC层的晶片的红外反射光谱与反射器的红外反射光谱之比被计算为找出具有≈0的波数向量k的T 2 声子的TO模式和LO模式的波数。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2008184361A METHOD FOR FORMING 3C-SiC SINGLE CRYSTAL FILM 审中-公开
标题翻译：形成3C-SiC单晶膜的方法
公开(公告)号：JP2008184361A
公开(公告)日：2008-08-14
申请号：JP2007019022
申请日：2007-01-30
申请人： Covalent Materials Corp , コバレントマテリアル株式会社
发明人： ABE YOSHIHISA , SUZUKI SHUNICHI , KOMIYAMA JUN , YOSHIDA AKIRA , NAKANISHI HIDEO
IPC分类号： C30B29/36 , C23C16/02 , C23C16/42 , C30B25/18 , H01L21/205
摘要： PROBLEM TO BE SOLVED: To provide a method for simply forming a high quality 3C-SiC single crystal film flat and free from an anti-phase domain on an Si single crystal substrate.
SOLUTION: The high quality 3C-SiC single crystal film is obtained by epitaxially growing a 3C-SiC single crystal on an Si single crystal substrate whose off angle from (001) plane direction is ≥0.2° and , after an anneal treatment of the Si single crystal substrate in a 100% hydrogen atmosphere.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种在Si单晶衬底上简单地形成平坦且无反相域的高质量3C-SiC单晶膜的方法。解决方案：通过在（001）面方向的偏角≥0.2°和<1°的Si单晶衬底上外延生长3C-SiC单晶并获得高品质3C-SiC单晶膜，在100％氢气氛中对Si单晶衬底进行退火处理之后，关闭方向为<100>。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2007266151A Compound semiconductor device 审中-公开
标题翻译：化合物半导体器件
公开(公告)号：JP2007266151A
公开(公告)日：2007-10-11
申请号：JP2006086844
申请日：2006-03-28
申请人： Covalent Materials Corp , コバレントマテリアル株式会社
发明人： KOMIYAMA JUN , ABE YOSHIHISA , SUZUKI SHUNICHI , NAKANISHI HIDEO
IPC分类号： H01L29/12 , H01L21/336 , H01L29/739 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a highly efficient compound semiconductor device with less energy loss. SOLUTION: An n-type low carrier concentration layer 2 with a carrier concentration as ≥10 11 /cm 3 and ≤10 16 /cm 3 , a p-type layer 3 with the carrier concentration as ≥10 11 /cm 3 and ≤10 21 /cm 3 , and an n-type high carrier concentration layer 4 with the carrier concentration ≥10 16 /cm 3 and ≤10 21 /cm 3 , are sequentially laminated on a low resistance substrate 1. The respective layers 2-4 are made to be 3C-SiC single crystal with the fault density of not more than 10 4 /cm 2 concerning a micropipe, a double-positioning domain, an anti-phase domain, a stacking fault, and a twin band. The compound semiconductor device also includes: a gate insulating film 5 which contacts at least the p-type layer 3, a control electrode 6 which contacts the gate insulating film 5 and is electrically separated from the respective layers 2-4, an upper electrode 7 which contacts at least the p-type layer 3 and the n-type high carrier concentration layer 4, and a lower electrode 8 which contacts the low resistance substrate 1. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供具有较少能量损失的高效化合物半导体器件。
解决方案：载流子浓度为≥10 11 / cm 3 和≤10 16 的n型低载流子浓度层2 载体浓度为≥10 11 / cm 3 和≤10 21
的p型层3， / SP> / cm 3 / SP>，载流子浓度≥10 16 / cm 3的n型高载流子浓度层4和≤ 10 21 / cm 3 顺序层压在低电阻基板1上。各层2-4被制成3C-SiC单晶，其故障密度关于微管，双定位域，反相域，堆垛层错和双频带的不超过10 4 / cm 2 。复合半导体器件还包括：至少与p型层3接触的栅极绝缘膜5，与栅极绝缘膜5接触并与各层2-4电气分离的控制电极6，上部电极7 其至少接触p型层3和n型高载流子浓度层4，以及与低电阻基板1接触的下电极8.版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2011258782A Nitride semiconductor substrate 审中-公开
标题翻译：氮化物半导体基板
公开(公告)号：JP2011258782A
公开(公告)日：2011-12-22
申请号：JP2010132558
申请日：2010-06-10
申请人： Covalent Materials Corp , コバレントマテリアル株式会社
发明人： YOSHIDA AKIRA , KOMIYAMA JUN , ABE YOSHIHISA , OISHI KOJI , ERIGUCHI KENICHI , SUZUKI SHUNICHI
IPC分类号： H01L21/338 , H01L29/778 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To form a nitride semiconductor layer having normally-off operation between an intermediate layer and a device active layer, capable of achieving higher threshold voltage.SOLUTION: A nitride semiconductor substrate comprises: an intermediate layer that is formed on an Si single-crystal substrate, and is composed of a laminate structure of nitride semiconductors; a region 1 that is formed on the intermediate layer, and is composed of a nitride semiconductor having a composition of AlGaN (0≤x≤0.05), a thickness of 200 nm or more to 2000 nm or less, and a carbon concentration of 1×10atoms/cmor more to 1×10atoms/cmor less; a region 2 that is formed on the region 1, and is composed of a nitride semiconductor having a composition of AlGaN (0.1≤y≤1), a thickness of 0.2 nm or more to 100 nm or less, and a carbon concentration of 1×10atoms/cmor more to 1×10atoms/cmor less; and a device active layer of a nitride semiconductor formed on the region 2.
摘要翻译：要解决的问题：为了形成能够实现更高阈值电压的中间层和器件有源层之间具有常关操作的氮化物半导体层。解决方案：氮化物半导体衬底包括：形成在Si单晶衬底上的中间层，由氮化物半导体的叠层结构构成; 形成在中间层上的区域1，由具有组成为Al 1-x 的氮化物半导体构成的区域1， SB> N（0≥x≥0.05），厚度为200nm以上至2000nm以下，碳浓度为1×10原子/ cm×SP 3 或更小到1×10 21 atoms / cm 3 或更小; 形成在区域1上的区域2，由具有组成为Al 1-y的氮化物半导体构成的区域2， SB> N（0.1≥y≥1），厚度为0.2nm以上至100nm以下，碳浓度为1×10 6原子/ cm 2 SP 3 或更小到1×10 21 atoms / cm 3 或更小; 以及形成在区域2上的氮化物半导体的器件有源层。版权所有（C）2012，JPO＆INPIT

9. 发明专利

JP2011066360A Crystallinity evaluation method of epitaxial layer of hetero epitaxial wafer 审中-公开
标题翻译：异质外延层外延层的结晶评估方法
公开(公告)号：JP2011066360A
公开(公告)日：2011-03-31
申请号：JP2009218090
申请日：2009-09-18
申请人： Covalent Materials Corp , コバレントマテリアル株式会社
发明人： SHIRAI HIROSHI , KOMIYAMA JUN , ABE YOSHIHISA
IPC分类号： H01L21/66 , H01L21/205
摘要： PROBLEM TO BE SOLVED: To provide a method for evaluating the crystallinity of a compound semiconductor layer epitaxial-grown, in a simple manner, on a substrate by the value of LO-phonon band wave number of an infrared light. SOLUTION: By having a compound semiconductor crystal layer irradiated with an infrared beam by means of an infrared reflection method or an infrared transmission method, the LO-phonon band wave number is measured, and a residual stress of the semiconductor compound crystal layer is measured, based on a distortion in a direction vertical to a growth surface of X-ray diffraction about each of a plurality of samples, and the crystallinity of each semiconductor compound crystal layer of the plurality of samples is evaluated by using an AFM image. Among the samples which are decided as having crystallinity is superior by the evaluation, the sample whose LO-phonon band wave number is lowest is set as a reference value. When the LO-phonon band wave number acquired by irradiating the compound semiconductor crystal layer of evaluation object with the infrared light by means of the infrared reflection method or the infrared transmission method exceeds the reference value, the compound semiconductor crystal layer of evaluation object is decided as having superior crystallinity by the crystallinity evaluation method of the compound semiconductor crystal layer. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过红外光的LO-声子带波数的值，以简单的方式在衬底上评估外延生长的化合物半导体层的结晶度的方法。解决方案：通过利用红外反射法或红外线透射法对红外光束照射化合物半导体晶体层，测量LO声子带波数，并且半导体化合物晶体层的残留应力基于与多个样品中的每一个相邻的X射线衍射的生长面的垂直方向的变形，并且通过使用AFM图像来评价多个样品的各半导体化合物晶体层的结晶度。通过评价判断为具有结晶性的样品中，将LO-声子带波数最低的样品设定为基准值。当通过用红外反射法或红外线透射法用红外光照射评估对象的化合物半导体晶体层而获得的LO声子波段数超过基准值时，决定评估对象的化合物半导体晶体层通过化合物半导体晶体层的结晶度评价方法具有优异的结晶度。版权所有（C）2011，JPO＆INPIT

10. 发明专利

JP2010251738A Nitride semiconductor epitaxial substrate 有权
标题翻译：氮化物半导体外延衬底
公开(公告)号：JP2010251738A
公开(公告)日：2010-11-04
申请号：JP2010071381
申请日：2010-03-26
申请人： Covalent Materials Corp , コバレントマテリアル株式会社
发明人： OISHI KOJI , KOMIYAMA JUN , ERIGUCHI KENICHI , ABE YOSHIHISA , YOSHIDA AKIRA , SUZUKI SHUNICHI
IPC分类号： H01L21/338 , C30B29/38 , H01L21/205 , H01L29/778 , H01L29/812 , H01L33/32 , H01S5/323
摘要： PROBLEM TO BE SOLVED: To provide a nitride semiconductor epitaxial substrate having a buffer structure with excellent manufacturing efficiency, wherein cracking of a device active layer is suppressed and while improvement in crystallinity such as reduction in dislocation density is achieved, warpage accompanying film thickening of a nitride semiconductor is suppressed. SOLUTION: The nitride semiconductor epitaxial substrate includes: an Si substrate 1; a first multilayer buffer region 3, wherein an Al a Ga 1-a N (0.9≤a≤1.0) single-crystal layer 31 of 2 to 10 nm in thickness and an Al b Ga 1-b N (0≤b≤0.1) single-crystal layer 32 of 10 to 30 nm in thickness are alternately and repeatedly laminated; a second multilayer buffer region 4, wherein an Al c Ga 1-c N (0.9≤c≤1.0) single-crystal layer 41 of 2 to 10 nm in thickness and an Al d Ga 1-d N (0≤d≤0.1) single-crystal layer 42 of 200 to 500 nm in thickness are alternately and repeatedly laminated; a GaN single-crystal layer 5; and an Al x Ga 1-x N (0≤x≤1) single-crystal layer 6. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了提供具有优良制造效率的缓冲结构的氮化物半导体外延基板，其中抑制了器件活性层的裂纹，并且在获得诸如位错密度降低的结晶度的改善的同时，伴随膜的翘曲氮化物半导体的增厚被抑制。解决方案：氮化物半导体外延衬底包括：Si衬底1; 第一多层缓冲区域3，其中厚度为2至10nm的Al（SB）a N a（0.9≤a≤1.0）单晶层31和交替重复地层叠10〜30nm厚度的Al b N（0≤b≤0.1）单晶层32，第二多层缓冲区域4，其中厚度为2至10nm的AlSiBeNi（0.9≤c≤1.0）单晶层41和交替重复地层叠厚度为200〜500nm的Al d Ga（1≤d≤N≤0.0≤0.1）单晶层42， GaN单晶层5; 和（C）2011，JPO＆INPIT（C）2011（日本专利）＆lt; SB＆gt;＆lt; SB＆gt;

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式