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1. 发明专利

JP2009238812A Inspecting method for compound semiconductor substrate 审中-公开
标题翻译：复合半导体衬底的检查方法
公开(公告)号：JP2009238812A
公开(公告)日：2009-10-15
申请号：JP2008079863
申请日：2008-03-26
申请人： Covalent Materials Corp , National Institute For Materials Science , コバレントマテリアル株式会社 , 独立行政法人物質・材料研究機構
发明人： UCHIMARU TOMONORI , KANAI HIDEYUKI , KOMIYAMA JUN , SUZUKI SHUNICHI , OSADA MINORU
IPC分类号： H01L21/66 , H01S5/00
摘要： PROBLEM TO BE SOLVED: To provide an inspecting method for a compound semiconductor substrate, in which quality is evaluated with high precision during inspection on a compound semiconductor substrate having a multilayer structure.
SOLUTION: The inspecting method for the compound semiconductor substrate 10 having a buffer layer and a GaN layer stacked in order on a semiconductor substrate includes a step (S1) of exposing a cross section in the stacking direction of the buffer layer and GaN layer, a step (S2) of irradiating the exposed cross section with laser light and evaluating stress at three points of the buffer layer and GaN layer in the section, and the interface between the buffer layer and GaN layer, and a step (S3) of plotting stress values of the stress at the three points on a coordinate surface showing stress values on its longitudinal axis and measurement positions on its lateral axis, and determining whether the compound semiconductor substrate 10 is good or not based on positions of the three plotted points on the coordinate surface.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种化合物半导体衬底的检查方法，其中在具有多层结构的化合物半导体衬底的检查期间以高精度评估质量。解决方案：具有在半导体衬底上依次堆叠的缓冲层和GaN层的化合物半导体衬底10的检查方法包括：在缓冲层的层叠方向上暴露横截面的步骤（S1）和GaN 层，步骤（S2），用激光照射暴露的横截面，并评估该截面中的缓冲层和GaN层的三个点以及缓冲层和GaN层之间的界面的应力，以及步骤（S3）绘制在坐标表面上的三个点上的应力的应力值，显示其纵轴上的应力值及其横轴上的测量位置，并且基于三个绘制点的位置来确定化合物半导体衬底10是否良好在坐标面上。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2009065025A Compound semiconductor substrate 审中-公开
标题翻译：化合物半导体基板
公开(公告)号：JP2009065025A
公开(公告)日：2009-03-26
申请号：JP2007232632
申请日：2007-09-07
申请人： Covalent Materials Corp , National Institute For Materials Science , コバレントマテリアル株式会社 , 独立行政法人物質・材料研究機構
发明人： KOMIYAMA JUN , SUZUKI SHUNICHI , NAKANISHI HIDEO , UCHIMARU TOMONORI , KANAI HIDEYUKI , OSADA MINORU
IPC分类号： H01L21/20 , C30B29/38 , H01L21/205 , H01L21/338 , H01L29/778 , H01L29/812
摘要： PROBLEM TO BE SOLVED: To provide a compound semiconductor substrate having a GaN active layer which is stress free as a whole by finding a simple method for measuring stress using Raman spectroscopy and controlling the stress in a buffer layer based on it.
SOLUTION: On a base substrate 1 composed of any one of hexagonal SiC with a thickness of 100-1,000 μm, single crystal Si or a cubic SiC layer formed on the single crystal Si, a buffer layer 2, and a GaN active layer 3 with a thickness of 0.5-5 μm are laminated sequentially. The buffer layer 2 is constituted of an Al
y Ga
1-y N single crystal layer (0.2≤y≤0.3)2b-1 with a thickness of 3-250 nm formed on an Al
x Ga
1-x N single crystal layer (0.5 x Ga
1-x N single crystal layer 2a-n with a thickness of 3-250 nm and an Al
z Ga
1-z N single crystal layer (0≤z
摘要翻译：要解决的问题：提供一种具有GaN活性层的化合物半导体衬底，其通过使用拉曼光谱法测量应力的简单方法并基于其控制缓冲层中的应力，从而整体上无应力。解决方案：在由任何一种厚度为100-1,000μm的六方晶系SiC构成的基底基板1上，单晶Si或形成在单晶Si上的立方SiC层，缓冲层2和GaN活性物质依次层叠厚度为0.5〜5μm的层3。缓冲层2由厚度为3-250nm的Al Y Ga 1-y / SB> N单晶层（0.2≤y≤0.3）2b-1构成形成在厚度为3-250nm的Al x Ga 1-x N N单晶层（0.5 x Ga 1-x N单晶层2a-n >0≤z<0.5）2c-n，厚度为3-250nm。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2009057233A Method for evaluating compound semiconductor substrate, method for producing the same, and the compound semiconductor substrate 审中-公开
标题翻译：用于评价化合物半导体基板的方法，其制造方法和化合物半导体基板
公开(公告)号：JP2009057233A
公开(公告)日：2009-03-19
申请号：JP2007225054
申请日：2007-08-31
申请人： Covalent Materials Corp , National Institute For Materials Science , コバレントマテリアル株式会社 , 独立行政法人物質・材料研究機構
发明人： UCHIMARU TOMONORI , KANAI HIDEYUKI , KOMIYAMA JUN , SUZUKI SHUNICHI , NAKANISHI HIDEO , OSADA MINORU
IPC分类号： C30B29/38 , G01N21/65
摘要： PROBLEM TO BE SOLVED: To provide a method for evaluating a compound semiconductor substrate where, for producing a gallium nitride based compound semiconductor substrate of high quality, a fine crystal defect regarding a gallium nitride film can be easily confirmed at high precision using Raman spectroscopy, to provide a method for producing the same, and to provide the compound semiconductor substrate.
SOLUTION: Regarding the compound semiconductor substrate comprising a gallium nitride film, in the Raman spectroscopy spectra of scattered light obtained when the gallium nitride film is irradiated with monochromatic light with the excitation wavelength of 350 to 800 nm, by the appearance of the main peak in the region with the wave number of 565 to 570 cm
-1 and subpeaks caused by a crystal defect with the wave number of 100 to 700 cm
-1 , the presence of a crystal defect in the gallium nitride film is confirmed.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种用于评价化合物半导体衬底的方法，其中为了制造高质量的氮化镓基化合物半导体衬底，可以高精度地容易地确认关于氮化镓膜的微细晶体缺陷拉曼光谱法，以提供其制造方法，并提供化合物半导体衬底。解决方案：关于包含氮化镓膜的化合物半导体衬底，在氮化镓膜用激发波长为350至800nm的单色光照射时获得的散射光的拉曼光谱中，通过外观波数为565〜570cm -1的区域的主峰，由波数为100〜700cm -1的晶体缺陷引起的亚峰，证实在氮化镓膜中存在晶体缺陷。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2008282861A Corrosive member and its production process 审中-公开
标题翻译：腐蚀性成员及其生产工艺
公开(公告)号：JP2008282861A
公开(公告)日：2008-11-20
申请号：JP2007123464
申请日：2007-05-08
申请人： Covalent Materials Corp , コバレントマテリアル株式会社
发明人： UCHIMARU TOMONORI , KANAI HIDEYUKI , YOKOGAWA MASAYA , SAITO WATARU , AZUMA SHINYA
IPC分类号： H01L21/205 , C23C16/42 , C23C16/56 , H01L21/3065 , H01L21/683
摘要： PROBLEM TO BE SOLVED: To provide a corrosion resistant member having a high purity SiC film ensuring high corrosion resistance formed on the front surface of a carbon base material. SOLUTION: In the corrosion resistant member, an SiC film having a crystal structure of 3C, 6H or 4H is provided on the front surface of a carbon base material wherein the ratio of 6H or 4H on the top surface of the SiC film is larger than that on the carbon base material side surface. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有高纯度SiC膜的耐腐蚀构件，确保在碳基材的前表面上形成的高耐腐蚀性。解决方案：在耐腐蚀构件中，在碳基材的前表面上提供具有3C，6H或4H晶体结构的SiC膜，其中在SiC膜的顶表面上的6H或4H比例大于碳基材料侧表面上的尺寸。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2010083695A Translucent ceramic 审中-公开
标题翻译：透明陶瓷
公开(公告)号：JP2010083695A
公开(公告)日：2010-04-15
申请号：JP2008252848
申请日：2008-09-30
申请人： Covalent Materials Corp , コバレントマテリアル株式会社
发明人： UCHIMARU TOMONORI , KANAI HIDEYUKI , NAITO YOSHIYUKI
IPC分类号： C04B35/115 , C04B35/44
摘要： PROBLEM TO BE SOLVED: To provide a translucent ceramic stably colored to yellow orange even in a small dope amount. SOLUTION: The translucent ceramic is essentially composed of alumina comprising Fe (iron) and Cr (chromium), and in which the Fe content is 0.7 to 2.0 ppm and the Cr content is 0.7 to 20 ppm, or the translucent ceramic is essentially composed of Y 3 Al 5 O 12 (YAG) and is characterized in that the contents of Fe and Cr are 0.5 to 20 ppm, respectively. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供即使在很小的掺杂量下稳定地着色成黄橙色的半透明陶瓷。解决方案：半透明陶瓷基本上由包含Fe（铁）和Cr（铬）的氧化铝组成，其中Fe含量为0.7至2.0ppm，Cr含量为0.7至20ppm，或者半透明陶瓷为基本上由Y SB 3（YAG）组成，其特征在于Fe和Cr的含量为0.5〜20ppm，分别。版权所有（C）2010，JPO＆INPIT

6. 发明专利

JP2008109012A Evaluation method and evaluation apparatus for semiconductor wafer 审中-公开
标题翻译：用于半导体波形的评估方法和评估装置
公开(公告)号：JP2008109012A
公开(公告)日：2008-05-08
申请号：JP2006292314
申请日：2006-10-27
申请人： Covalent Materials Corp , コバレントマテリアル株式会社
发明人： KANAI HIDEYUKI , MATSUSHITA YOSHIAKI , TAKEDA RYUJI , NAGAHAMA HIROMI , HIRASAWA MANABU
IPC分类号： H01L21/66 , G01N21/65
摘要： PROBLEM TO BE SOLVED: To provide an evaluation method and evaluation apparatus for a semiconductor wafer capable of evaluating the surface structure of a semiconductor wafer having a level difference (step) structure whose flat surface (terrace) is a crystal plane within a short time on a wide range.
SOLUTION: The evaluation method for a semiconductor wafer having a level difference (step) structure whose flat surface (terrace) is a crystal plane comprises a procedure of irradiating the semiconductor wafer by scanning the surface thereof with a near-field light, a procedure of receiving the Raman scattering light generated from the semiconductor wafer, a procedure of deriving the Raman spectrum by analyzing the received Raman scattering light with a spectrometer, and a procedure of calculating the width of the flat surface (terrace width) from the derived Raman spectrum, while the evaluation apparatus achieves the method thereof.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决问题的方案：提供一种能够评价半导体晶片的表面结构的评价方法和评估装置，所述半导体晶片具有平面（平台）为平面内的晶面的水平差（台阶）结构，短时间在广泛的范围。解决方案：具有平面（平台）为晶面的电平差（台阶）结构的半导体晶片的评估方法包括通过用近场光扫描半导体晶片的表面来照射半导体晶片的步骤，接收从半导体晶片产生的拉曼散射光的过程，通过用光谱仪分析所接收的拉曼散射光来导出拉曼光谱的过程，以及从衍生的平面（宽度）计算平面宽度的步骤拉曼光谱，而评价装置达到其方法。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2008230932A Mold for casting silicon and its manufacturing method 有权
标题翻译：铸造硅及其制造方法的模具
公开(公告)号：JP2008230932A
公开(公告)日：2008-10-02
申请号：JP2007075719
申请日：2007-03-23
申请人： Covalent Materials Corp , コバレントマテリアル株式会社
发明人： UCHIMARU TOMONORI , KANAI HIDEYUKI
IPC分类号： C01B33/02
摘要： PROBLEM TO BE SOLVED: To provide a mold for casting silicon, the releasability of which is improved much more, the inside surface layer of which is prevented from being exfoliated and dropped out and in which a silicon ingot having no crack can be casted in high yield and to provide a method for manufacturing the mold for casting silicon.
SOLUTION: The mold for casting silicon is manufactured, which has on the inside surface thereof a mold release layer formed by carrying out the steps of: dispersing powders containing aluminum nitride or cerium oxide in a solvent to prepare slurry; applying the prepared slurry to the inside surface of the mold for casting silicon; and drying the applied slurry.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种用于铸造硅的模具，其脱模性得到改善，其内表面层被防止脱落脱落，并且其中没有裂纹的硅锭可以是以高产量铸造，并提供一种制造用于铸造硅的模具的方法。解决方案：制造用于铸造硅的模具，其内表面具有通过以下步骤形成的脱模层：将含有氮化铝或氧化铈的粉末分散在溶剂中以制备浆料; 将制备的浆料施加到用于铸造硅的模具的内表面; 并干燥所施加的浆料。版权所有（C）2009，JPO＆INPIT

8. 发明专利

JP2008135732A Method for manufacturing semiconductor substrate 审中-公开
标题翻译：制造半导体基板的方法
公开(公告)号：JP2008135732A
公开(公告)日：2008-06-12
申请号：JP2007277700
申请日：2007-10-25
申请人： Covalent Materials Corp , コバレントマテリアル株式会社
发明人： ISOGAI HIROMICHI , TAKEDA RYUJI , KANAI HIDEYUKI , MATSUSHITA YOSHIAKI , NAGAHAMA HIROMI , HIRASAWA MANABU , TOYODA EIJI , SENDA TAKESHI , NARITA AKIKO , SENSAI KOJI
IPC分类号： H01L21/02 , H01L21/322
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor substrate for suppressing the generation of any crystal defect in the case of creating a region having different crystal plane orientation on the substrate surface by using a semiconductor substrate where a semiconductor layer having the different crystal plane orientation is laminated.
SOLUTION: This method for manufacturing a semiconductor substrate includes: a process for preparing a first semiconductor wafer having first crystal plane orientation on the surface; a process for preparing a second semiconductor wafer having second crystal plane orientation different from the first crystal plane orientation on the surface; a process for carrying out heat treatment to either the first or second semiconductor wafer in the atmosphere of reduction gas, inert gas, or the mixed gas of the reduction gas and the inert gas in temperature which is 1,025°C or more and 1,250°C or less, and in a time which is 30 seconds or more and 2 hours or less; a process for joining the first and second semiconductor wafers; and a process for forming a semiconductor layer for device formation by working the second semiconductor wafer to predetermined width.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供一种制造半导体衬底的方法，用于在通过使用半导体衬底的半导体衬底上产生在衬底表面上产生具有不同晶面取向的区域的情况下抑制任何晶体缺陷的产生，具有不同的晶面取向层压。解决方案：这种制造半导体衬底的方法包括：制备在表面上具有第一晶面取向的第一半导体晶片的工艺; 制备具有与表面上的第一晶面取向不同的第二晶面取向的第二半导体晶片的工艺; 在还原气体，惰性气体或还原气体和惰性气体的混合气体中的温度为1025℃以上且1250℃以下，对第一或第二半导体晶片进行热处理的工序在30秒以上2小时以下的时间内，用于接合第一和第二半导体晶片的工艺; 以及通过将第二半导体晶片加工成预定宽度来形成用于器件形成的半导体层的工艺。版权所有（C）2008，JPO＆INPIT

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