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1. 发明专利

JP2005311184A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2005311184A
公开(公告)日：2005-11-04
申请号：JP2004128494
申请日：2004-04-23
申请人： Semiconductor Leading Edge Technologies Inc , 株式会社半導体先端テクノロジーズ
发明人： URE PATRICE
IPC分类号： H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing semiconductor devices that can accurately control channel characteristics.
SOLUTION: This manufacturing method comprises six processes of (1) injecting impurities into the surface of a semiconductor substrate 11 to form a diffusion layer 14, (2) activating the diffusion layer 14 through the first thermal processing, (3) etching the diffusion layer 14 to form a trench 16, (4) forming a semiconductor layer 17 within the trench 16, (5) forming a gate insulting film 18 on the semiconductor 17, and (6) forming a gate electrode 19 on the gate insulting film 18.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种可以精确控制通道特性的半导体器件的制造方法。解决方案：该制造方法包括（1）将杂质注入到半导体衬底11的表面中以形成扩散层14的六个工艺，（2）通过第一热处理激活扩散层14，（3）蚀刻扩散层14形成沟槽16，（4）在沟槽16内形成半导体层17，（5）在半导体17上形成栅极绝缘膜18，以及（6）在栅极绝缘上形成栅电极19 电影18.版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2005265676A Sample measuring method using atomic force microscope and sample measuring system therefor 审中-公开
标题翻译：使用原子力显微镜和其样品测量系统的样品测量方法
公开(公告)号：JP2005265676A
公开(公告)日：2005-09-29
申请号：JP2004080013
申请日：2004-03-19
申请人： Semiconductor Leading Edge Technologies Inc , 株式会社半導体先端テクノロジーズ
发明人： TANAKA YOSHIYUKI
IPC分类号： G01Q30/20 , G01Q60/24 , G01N13/16
摘要： PROBLEM TO BE SOLVED: To enhance the measuring precision of an atomic force microscope by destaticizing a sample efficiently without applying load to a sample measuring system when the sample is measured using the atomic force microscope.
SOLUTION: A static eliminator 4 and a charge monitor 3 are arranged and the charge monitor 3 is controlled on the basis of the position of the probe 2 of the atomic force microscope by a monitor position control means 7 so as to measure the charge quantity in the periphery of the position of the probe 2 of the sample 1. For example, the position of the charge monitor 3 is controlled so as to always arrange the charge monitor 3 in the vicinity of the probe 2 or the monitor positioned in the vicinity of the probe 2 is selected from a plurality of the charge monitors and charge quantity is measured by the monitor. A static elimination control means 8 is constituted so as to operate the static eliminator 4 for a definite time when the charge quantity measured by the charge monitor 3 exceeds a predetermined value to destaticize the sample.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：当使用原子力显微镜测量样品时，通过使样品有效地对样品测量系统施加负载来有效地对样品进行去电，来提高原子力显微镜的测量精度。
解决方案：安排静电消除器4和充电监视器3，并且通过监视器位置控制装置7基于原子力显微镜的探针2的位置来控制充电监视器3，以便测量例如，电荷监视器3的位置被控制为总是将电荷监视器3布置在探针2附近或位于探针2的监视器的附近从多个充电监视器中选择探头2的附近，并且由监视器测量充电量。当静电消除控制装置8被构造成当由充电监视器3测量的充电量超过预定值以使样本静电时，将静电消除器4操作一定时间。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2005251697A Scanning electron microscope and acceleration voltage optimization method in scanning electron microscope 审中-公开
标题翻译：扫描电子显微镜扫描电子显微镜和扫描电子显微镜的加速电压优化方法
公开(公告)号：JP2005251697A
公开(公告)日：2005-09-15
申请号：JP2004064484
申请日：2004-03-08
申请人： Semiconductor Leading Edge Technologies Inc , 株式会社半導体先端テクノロジーズ
发明人： MITA ISAO
IPC分类号： H01J37/22 , H01J37/04 , H01J37/28
摘要： PROBLEM TO BE SOLVED: To improve dimensional inspection accuracy and reproducibility of a scanning electron microscope.
SOLUTION: Various electron beams 12 with accelerating voltages impressed on an electron gun 11 from an accelerating voltage impressing means 13 changed are irradiated, each secondary electron emitted thereby from a sample 16 is detected by a secondary electron detecting means 19, each contrast is detected by a contrast detecting means 22 based on the secondary electron detected, and an optimum accelerating voltage at which the contrast gets the largest is determined based on each accelerating voltage and the contrast detected. Afterwards, the electron beams 12 accelerated by the optimally accelerated accelerating voltage is irradiated on the sample 16 to carry out dimensional measurement of an actual pattern.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提高扫描电子显微镜的尺寸检查精度和再现性。照射从加速电压施加装置13施加在电子枪11上的加速电压的各种电子束12变化，由二次电子检测装置19检测从样品16发射的二次电子，每个对比度基于检测到的二次电子的对比度检测装置22检测出，并且基于每个加速电压和检测到的对比度来确定对比度最大的最佳加速电压。然后，通过最佳加速的加速电压加速的电子束12被照射在样品16上，以进行实际图案的尺寸测量。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2005223290A Patterning method 审中-公开
标题翻译：绘图方法
公开(公告)号：JP2005223290A
公开(公告)日：2005-08-18
申请号：JP2004032596
申请日：2004-02-09
申请人： Semiconductor Leading Edge Technologies Inc , 株式会社半導体先端テクノロジーズ
发明人： IRIE SHIGEO
IPC分类号： G03F7/11 , G03F7/40 , H01L21/027 , H01L21/3065
摘要： PROBLEM TO BE SOLVED: To provide a method for forming a fine rectangular resist pattern having satisfactory resistance to dry etching with reproducibility.
SOLUTION: The patterning method comprises a step for baking a first organic material film 10 formed on an underlying film 2 in a semiconductor device fabrication process, a step for baking a second organic material film 11 formed on the first organic material film 10, a step for baking the second organic material film 11, by exposing it with a single wavelength through a photomask, a step for forming a second organic material film pattern, by developing the second organic material film 11, and a step for forming a desired pattern by etching the underlying film, using the second organic material film pattern as a mask, wherein an acid additive is introduced into the first organic material film.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种形成具有令人满意的具有可再现性的干蚀刻耐久性的精细矩形抗蚀剂图案的方法。解决方案：图案化方法包括在半导体器件制造工艺中烘焙形成在下面的膜2上的第一有机材料膜10的步骤，用于焙烧形成在第一有机材料膜10上的第二有机材料膜11的步骤第二有机材料膜11的显影步骤，通过使光掩模暴露于单一波长，通过显影第二有机材料膜11形成第二有机材料膜图案的步骤，以及形成期望的通过蚀刻底层膜，使用第二有机材料膜图案作为掩模，其中将酸添加剂引入到第一有机材料膜中。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2005210076A Deposition method of silicon nitride film, and manufacturing method of semiconductor device using the deposition method 审中-公开
标题翻译：硅酸盐膜的沉积方法和使用沉积方法的半导体器件的制造方法
公开(公告)号：JP2005210076A
公开(公告)日：2005-08-04
申请号：JP2004338459
申请日：2004-11-24
申请人： L'air Liquide Sa Pour L'etude & L'exploitation Des Procede S Georges Claude , Semiconductor Leading Edge Technologies Inc , レール・リキード−ソシエテ・アノニム・ア・ディレクトワール・エ・コンセイユ・ドゥ・スールベイランス・プール・レテュード・エ・レクスプロワタシオン・デ・プロセデ・ジョルジュ・クロード , 株式会社半導体先端テクノロジーズ
发明人： HOSHI TAKASHI , SAITO TAKESHI , KIMURA TAKAKO , DUSSARAT CHRISTIAN , YANAGIDA KAZUTAKA
IPC分类号： C23C16/34 , H01L21/318
CPC分类号： C23C16/345 , H01L21/3185
摘要： PROBLEM TO BE SOLVED: To improve quality of a low-temperature silicon nitride film formed by LPCVD. SOLUTION: In LPCVD apparatus 10, silicon source materials (SiH 2 Cl 2 , SiCl 4 , SiCl 6 and the like) are supplied from an injector 11, and a mixed gas of ammonia (NH 3 ) and monomethylamine (CH 3 NH 2 ) as nitrogen source materials are supplied from an injector 12, and a silicon nitride film is thus formed on a silicon wafer 14 arranged on a boat 13. By adding monomethylamine to the source materials, a leakage characteristic of the film is improved even at low temperature (600°C to 450°C), resulting in improvement in film quality. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提高通过LPCVD形成的低温氮化硅膜的质量。解决方案：在LPCVD装置10中，硅源材料（SiH 2 2 ，SiCl 4 ，SiCl < SB>等）从喷射器11供给，并且将氨（NH 3 SB 3）和一甲胺（CH 3 SB SB）的混合气体 >），由喷射器12供给氮源材料，由此在设置在舟皿13上的硅晶片14上形成氮化硅膜。通过向源材料添加一甲胺，即使在低温（600℃〜450℃），膜质量提高。版权所有（C）2005，JPO＆NCIPI

6. 发明专利

JP2005209996A Method for manufacturing stencil mask and semiconductor device 审中-公开
标题翻译：制造薄膜掩模和半导体器件的方法
公开(公告)号：JP2005209996A
公开(公告)日：2005-08-04
申请号：JP2004016853
申请日：2004-01-26
申请人： Semiconductor Leading Edge Technologies Inc , 株式会社半導体先端テクノロジーズ
发明人： SAKAGAMI HIROSHI
IPC分类号： G03F1/20 , H01L21/027 , G03F1/16
摘要： PROBLEM TO BE SOLVED: To conduct exposure by an EPL without using a complementary segment mask and without conducting double exposure for a pattern requiring the complementary segment. SOLUTION: It is designed that the pattern 23 requiring the complementary segement is arranged in a fuzzy boundary region 43 and the pattern is complementarily segmented between adjacent subfields 1 by the use of the fuzzy boundary. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：通过EPL进行曝光，而不使用互补区域掩模，而不需要对需要互补区段的图案进行双重曝光。解决方案：设计需要互补区段的图案23被布置在模糊边界区域43中，并且通过使用模糊边界在相邻子场1之间互补地分割图案。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2005209918A Wafer, data display method, and wafer region specifying method 审中-公开
标题翻译： WAFER，数据显示方法和WAFER REGION SPECIFYING方法
公开(公告)号：JP2005209918A
公开(公告)日：2005-08-04
申请号：JP2004015548
申请日：2004-01-23
申请人： Semiconductor Leading Edge Technologies Inc , 株式会社半導体先端テクノロジーズ
发明人： UCHIDA ITSURO
IPC分类号： H01L21/02
CPC分类号： H01L2223/54406 , H01L2223/5442 , H01L2223/54493
摘要： PROBLEM TO BE SOLVED: To provide a wafer easily to recognize data added to the wafer even after wafer treatment or with particles deposited to the wafer during treatment.
SOLUTION: The wafer 1 has a binary number information part 50 in its specified peripheral zone which expresses specified data with binary numbers using a plurality of dots. The information part 50 has micromarks 10 formed of the plurality of dots to express the data depending the presence or the absence of the micromarks 10.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：即使在晶片处理之后或者在处理期间沉积到晶片上的颗粒，也可以容易地提供晶片以识别添加到晶片的数据。解决方案：晶片1在其指定的外围区域中具有使用多个点表示具有二进制数的指定数据的二进制数信息部分50。信息部分50具有由多个点形成的微突起10，以根据存在或不存在微观声迹10来表示数据。（C）2005年，JPO和NCIPI

8. 发明专利

JP2005197567A Inspection method and equipment of charged particle beam transfer mask and charged particle beam transfer mask 审中-公开
标题翻译：充电粒子束传输掩模和充电颗粒束传输掩模的检查方法和设备
公开(公告)号：JP2005197567A
公开(公告)日：2005-07-21
申请号：JP2004003991
申请日：2004-01-09
申请人： Semiconductor Leading Edge Technologies Inc , 株式会社半導体先端テクノロジーズ
发明人： YAMAMOTO JIRO
IPC分类号： G03F1/84 , G03F1/86 , H01L21/027 , G03F1/16
摘要： PROBLEM TO BE SOLVED: To provide an inspection method of a charged particle beam transfer mask capable of performing quantitative measurement of contamination of the mask easily and surely through an extremely simple arrangement, and to provide inspection equipment and the charged particle beam transfer mask. SOLUTION: In the inspection method of a charged particle beam transfer mask being employed as a mask for irradiating an object with a charged particle beam, variation in size of an aperture provided in the charged particle beam transfer mask is judged by measuring variation in dosage of a charged particle beam passing through the aperture. Contamination of the mask can be grasped easily and surely by measuring and managing a mask current passing through a predetermined aperture pattern provided in a predetermined mask. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够通过非常简单的布置容易且可靠地进行定量测量面罩污染的带电粒子束传递掩模的检查方法，并提供检查设备和带电粒子束传递面具。＆lt; P＆gt;解决方案：在带电粒子束传递掩模的检查方法中，作为用带电粒子束照射物体的掩模，通过测量变化来判断带电粒子束传递掩模中设置的孔的尺寸变化在通过孔的带电粒子束的剂量中。通过测量和管理通过预定掩模中提供的预定孔径图案的掩模电流，可以容易且可靠地掌握掩模的污染。版权所有（C）2005，JPO＆NCIPI

9. 发明专利

JP2005191482A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005191482A
公开(公告)日：2005-07-14
申请号：JP2003434367
申请日：2003-12-26
申请人： Semiconductor Leading Edge Technologies Inc , 株式会社半導体先端テクノロジーズ
发明人： KAMIYAMA SATOSHI
IPC分类号： H01L21/336 , H01L21/28 , H01L21/314 , H01L21/316 , H01L29/51 , H01L29/78
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/3141 , H01L21/3143 , H01L21/31604 , H01L21/31608 , H01L21/31645 , H01L29/513 , H01L29/517 , H01L29/518
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having C-V characteristic which is equivalent to ideal C-V characteristic by controlling the metal concentration in a metal silicate film provided to the uppermost layer of a high dielectric constant film. SOLUTION: In the semiconductor device formed by forming a gate electrode 7b through a gate insulating film on a silicon substrate 1, the gate insulating film is constituted by laminating a silicon oxide film 4a formed on the silicon substrate 1, an Hf silicate film 5a formed on the silicon oxide film 4a, and a nitrogen containing Hf silicate film 6a which is formed on the Hf silicate film 5a and contains Hf at a peak concentration of 1 atomic% or more and 30 atomic% or less and contains nitrogen at a peak concentration of 10 atomic% or more and 30 atomic% or less. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：通过控制设置在高介电常数膜的最上层的金属硅酸盐膜中的金属浓度，提供具有相当于理想C-V特性的C-V特性的半导体器件。解决方案：在通过在硅衬底1上通过栅极绝缘膜形成栅极电极7b形成的半导体器件中，栅极绝缘膜通过层叠形成在硅衬底1上的氧化硅膜4a，Hf硅酸盐形成在氧化硅膜4a上的膜5a和形成在Hf硅酸盐膜5a上的含氮Hf硅酸盐膜6a，并且含有峰值浓度为1原子％以上且30原子％以下的Hf，并且含有氮峰值浓度为10原子％以上且30原子％以下。版权所有（C）2005，JPO＆NCIPI

10. 发明专利

JP2005191291A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005191291A
公开(公告)日：2005-07-14
申请号：JP2003430935
申请日：2003-12-25
申请人： Semiconductor Leading Edge Technologies Inc , 株式会社半導体先端テクノロジーズ
发明人： OTSUKA NOBUYUKI , OGAWA SHINICHI , OKAMURA HIROSHI
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52
摘要： PROBLEM TO BE SOLVED: To form a metal film or a metal compound film while securing a high adhesion property on a porous insulating film. SOLUTION: The porous insulating film is formed on a substrate, and the metal film or the metal compound film is formed on the insulating film. In this case, conditions of the film formation of the metal film or the like are changed, and a diffusion layer in which metal or a metal compound included in the metal film or the metal compound film is diffused to the insulating film is formed between the metal film or the metal compound, and the insulating film. The diffusion layer increases the adhesion property between the metal film and the porous insulating film. COPYRIGHT: (C)2005,JPO&NCIPI

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