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1. 发明专利

JP2005191291A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005191291A
公开(公告)日：2005-07-14
申请号：JP2003430935
申请日：2003-12-25
申请人： Semiconductor Leading Edge Technologies Inc , 株式会社半導体先端テクノロジーズ
发明人： OTSUKA NOBUYUKI , OGAWA SHINICHI , OKAMURA HIROSHI
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52
摘要： PROBLEM TO BE SOLVED: To form a metal film or a metal compound film while securing a high adhesion property on a porous insulating film. SOLUTION: The porous insulating film is formed on a substrate, and the metal film or the metal compound film is formed on the insulating film. In this case, conditions of the film formation of the metal film or the like are changed, and a diffusion layer in which metal or a metal compound included in the metal film or the metal compound film is diffused to the insulating film is formed between the metal film or the metal compound, and the insulating film. The diffusion layer increases the adhesion property between the metal film and the porous insulating film. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：在多孔绝缘膜上确保高附着性的同时形成金属膜或金属化合物膜。解决方案：多孔绝缘膜形成在基板上，金属膜或金属化合物膜形成在绝缘膜上。在这种情况下，金属膜等的成膜条件发生变化，并且在金属膜或金属化合物膜中包含的金属或金属化合物扩散到绝缘膜的扩散层形成在金属膜或金属化合物，以及绝缘膜。扩散层增加金属膜和多孔绝缘膜之间的粘附性。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2005142325A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005142325A
公开(公告)日：2005-06-02
申请号：JP2003376685
申请日：2003-11-06
申请人： Semiconductor Leading Edge Technologies Inc , 株式会社半導体先端テクノロジーズ
发明人： FURUYA AKIRA , OTSUKA NOBUYUKI , OGAWA SHINICHI , OKAMURA HIROSHI
IPC分类号： H01L21/00 , H01L21/316 , H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/522 , H01L23/532 , H01L29/40
CPC分类号： H01L21/76843 , H01L21/7682 , H01L21/76864 , H01L21/76877 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which uses, for an interlayer insulation film, a material having a low dielectric constant which can prevent the diffusion of an interconnection material, such as a barrier metal and Cu, and to provide its manufacturing method. SOLUTION: The semiconductor device comprises a substrate made of a semiconductor and an interconnection structure formed on the substrate. The interconnection structure includes a porous insulation film wherein the volume dominated by such pores that have a diameter of 0.6 nm or larger is 30% or lower, and a current-carrying portion formed of a conductor mainly made of metal. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种半导体器件，其对于层间绝缘膜使用具有低介电常数的材料，其可以防止诸如阻挡金属和Cu的互连材料的扩散，并且提供其制造方法。解决方案：半导体器件包括由半导体制成的衬底和形成在衬底上的互连结构。互连结构包括多孔绝缘膜，其中由直径为0.6nm或更大的这种孔占主导的体积为30％或更低，以及由主要由金属制成的导体形成的载流部分。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2005191471A Manufacturing method of semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2005191471A
公开(公告)日：2005-07-14
申请号：JP2003434196
申请日：2003-12-26
申请人： Semiconductor Leading Edge Technologies Inc , 株式会社半導体先端テクノロジーズ
发明人： OKAMURA HIROSHI , OTSUKA NOBUYUKI , FURUYA AKIRA , OGAWA SHINICHI
IPC分类号： H01L21/302 , H01L21/768
摘要： PROBLEM TO BE SOLVED: To remove a metal oxide film formed in a lower layer wiring surface by restraining deterioration of a low dielectric constant film and performance degradation of wiring.
SOLUTION: A second insulating film 12 is formed on a first insulating film 4 which is formed on a substrate and has metal wiring 6, and an opening 16 which passes through the second insulating film 12 and exposes a metal wiring surface is formed. Before a conductive member is embedded in the opening, an oxide film in the metal wiring surface is removed by using a reducing gas which has reducibility to the oxide film of the metal wiring surface formed by oxidation of metal wiring. Thereafter, the conductive member is embedded in the opening and wiring connected to the metal wiring is formed.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：通过抑制低介电常数膜的劣化和布线的性能劣化来去除形成在下层布线表面中的金属氧化物膜。解决方案：在形成在基板上并具有金属布线6的第一绝缘膜4上形成第二绝缘膜12，并且形成穿过第二绝缘膜12并露出金属布线表面的开口16 。在将导电构件嵌入开口内之前，通过使用与金属配线的氧化形成的金属布线面的氧化膜还原性的还原气体，去除金属布线面中的氧化膜。此后，将导电部件嵌入开口中，形成与金属布线相连接的布线。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2004363447A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2004363447A
公开(公告)日：2004-12-24
申请号：JP2003162042
申请日：2003-06-06
申请人： Semiconductor Leading Edge Technologies Inc , 株式会社半導体先端テクノロジーズ
发明人： OKAMURA HIROSHI , OTSUKA NOBUYUKI , SONE SHUJI
IPC分类号： H01L21/768 , H01L21/31 , H01L21/3205 , H01L23/52 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device by which a high resistance layer can be removed without changing the shapes of a via hole and a wiring groove.
SOLUTION: Plasma treatment of the high resistance layer 12 on the surface of a copper wiring layer 1 exposed to the bottom of the via hole 10 is carried out using etching gas containing reducing gas. The reducing gas can contain at least one in a group of gas consisting of hydrogen, ammonia and hydrazine. An interlayer insulating film 6 whose Young's modulus is 7 or more GPa and whose specific inductive capacity is less than 3 is used.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种制造半导体器件的方法，通过该方法可以在不改变通孔和布线槽的形状的情况下去除高电阻层。解决方案：使用含有还原气体的蚀刻气体进行暴露于通孔10的底部的铜布线层1的表面上的高电阻层12的等离子体处理。还原气体可以包含由氢，氨和肼组成的一组气体中的至少一种。使用杨氏模量为7以上GPa并且其微结构容量小于3的层间绝缘膜6。版权所有（C）2005，JPO＆NCIPI

5. 发明专利

JP2005209901A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005209901A
公开(公告)日：2005-08-04
申请号：JP2004015178
申请日：2004-01-23
申请人： Semiconductor Leading Edge Technologies Inc , 株式会社半導体先端テクノロジーズ
发明人： FURUYA AKIRA , OTSUKA NOBUYUKI , OKAMURA HIROSHI
IPC分类号： H01L21/768 , H01L21/312 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To restrain the diffusion of metal or the like and to secure the strength of a porous insulating film to a certain degree when the porous insulating film is employed as an interlayer insulating film.
SOLUTION: The porous insulating film comprising a first insulating material and having vacancies is formed on a sample substrate. A first coated film and a second coated film are formed on the surface of the porous insulating film. The first costed film is constructed by making a second insulating material invade the vacancies located in the vicinity of the surface of the porous insulating film. The second coated film is constructed using the second insulating material.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了抑制金属等的扩散，并且当使用多孔绝缘膜作为层间绝缘膜时，确保多孔绝缘膜的强度一定程度。解决方案：在样品基板上形成包括具有空位的第一绝缘材料的多孔绝缘膜。在多孔绝缘膜的表面上形成第一涂膜和第二涂膜。第一成品膜通过使第二绝缘材料侵入位于多孔绝缘膜表面附近的空位而构成。使用第二绝缘材料构造第二涂膜。版权所有（C）2005，JPO＆NCIPI

6. 发明专利

JP2005203569A Fabrication process of semiconductor device and semiconductor device 审中-公开
标题翻译：半导体器件和半导体器件的制造工艺
公开(公告)号：JP2005203569A
公开(公告)日：2005-07-28
申请号：JP2004008418
申请日：2004-01-15
申请人： Semiconductor Leading Edge Technologies Inc , 株式会社半導体先端テクノロジーズ
发明人： FURUYA AKIRA , OKAMURA HIROSHI , OTSUKA NOBUYUKI , OGAWA SHINICHI
IPC分类号： C23C16/34 , C23C16/52 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To strike a balance between adhesiveness and diffusion preventive properties of a barrier metal, and to improve controllability of composition in the film thickness direction.
SOLUTION: The fabrication process of a semiconductor device comprises a step for forming a TaN film on a substrate using Ta[N(CH
3 )
2 ]
5 gas and NH
3 gas for reducing the Ta[N(CH
3 )
2 ]
5 gas, and a step for forming a Ta film on the TaN film formed by the TaN film forming step using the Ta[N(CH
3 )
2 ]
5 gas and He/H
2 gas for reducing the Ta[N(CH
3 )
2 ]
5 gas without exposing the substrate to the atmosphere.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了在阻挡金属的粘附性和扩散防止性能之间达到平衡，并提高膜厚度方向上组成的可控性。解决方案：半导体器件的制造工艺包括使用Ta [N（CH 3 SBB）SB SB 2]在SBR上形成TaN膜的步骤。 5气体和NH 3 SB 3气体，用于还原Ta [N（CH 3 SB 3）2 SB SB 并且在TaN膜形成步骤中使用Ta [N（CH 3 SBB）SB SB 2]形成Ta膜的步骤。 5气体和He / H 2气体，用于还原Ta [N（CH 3 SBB）SB < / SB>气体，而不将基板暴露在大气中。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2005191290A Method for manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2005191290A
公开(公告)日：2005-07-14
申请号：JP2003430934
申请日：2003-12-25
申请人： Semiconductor Leading Edge Technologies Inc , 株式会社半導体先端テクノロジーズ
发明人： OTSUKA NOBUYUKI , FURUYA AKIRA , OKAMURA HIROSHI
IPC分类号： C23C16/30 , C23C16/44 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To form a thin film having improved properties by suppressing an increase in dielectric constant and a decrease in diffusion prevention function on a porous insulating film.
SOLUTION: In a film-formation method for forming a film made of metal or a metal compound on a porous insulating film having a void formed in a substrate, first a thin film in a state of a particle that is at least larger than the void is formed on the porous insulating film. Then, a first material containing at least one raw material in raw materials included in the metal or the metal compound is supplied into a treatment chamber. The first material in the treatment chamber is purged and allowed to react with a first material, and a second material for composing the metal or the metal compound of the film to be formed is supplied, and the second material in the treatment chamber is purged again. A thin film of a desired film thickness is formed by repeating a cycle composed of the supply of the first material, the supply of the second purged material, and purging.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：通过抑制介电常数的增加和多孔绝缘膜上的扩散防止功能的降低，形成具有改进性能的薄膜。解决方案：在具有在基板上形成的空隙的多孔绝缘膜上形成由金属或金属化合物制成的膜的成膜方法中，首先在至少较大的颗粒状态下形成薄膜比在多孔绝缘膜上形成空隙。然后，将包含在金属或金属化合物中的原料中的至少一种原料的第一材料供给到处理室。处理室中的第一材料被吹扫并允许与第一材料反应，并且供给用于构成待形成的膜的金属或金属化合物的第二材料，并且处理室中的第二材料再次被清除。通过重复由第一材料的供应，第二吹扫材料的供应和清洗组成的循环来形成所需膜厚度的薄膜。版权所有（C）2005，JPO＆NCIPI

8. 发明专利

JP2005203568A Fabrication process of semiconductor device, and semiconductor device 审中-公开
标题翻译：半导体器件的制造工艺和半导体器件
公开(公告)号：JP2005203568A
公开(公告)日：2005-07-28
申请号：JP2004008416
申请日：2004-01-15
申请人： Semiconductor Leading Edge Technologies Inc , 株式会社半導体先端テクノロジーズ
发明人： FURUYA AKIRA , YONEDA KATSUMI , OKAMURA HIROSHI , YOSHIE TORU , OTSUKA NOBUYUKI , OGAWA SHINICHI
IPC分类号： C23C16/42 , H01L21/312 , H01L21/768 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing diffusion of barrier metal into an interlayer dielectric and to provide its fabrication process.
SOLUTION: The fabrication process of a semiconductor device comprises a step (S104) for forming a porous insulation film 120 employing an insulating material on a substrate 100, a step (S108) for forming an opening 150 in the porous insulation film 120, a compound film forming step (S110) for forming an SiCH film 160 containing Si, C and H on the inner surface of the opening 150 formed by the opening forming step (S108), and a barrier metal film forming step (S114) for forming a barrier metal film 170 employing a barrier metal material in the opening 150 where the SiCH film 160 is formed on the inner surface by the compound film forming step.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供能够防止阻挡金属扩散到层间电介质中并提供其制造工艺的半导体器件。解决方案：半导体器件的制造工艺包括用于在衬底100上形成绝缘材料的多孔绝缘膜120的形成步骤（S104），在多孔绝缘膜120中形成开口150的步骤（S108），用于在由开口形成步骤（S108）形成的开口150的内表面上形成包含Si，C和H的SiCH膜160的复合膜形成步骤（S110）和用于在开口150中形成阻挡金属膜170，其中通过化合物膜形成步骤在内表面上形成SiCH膜160。版权所有（C）2005，JPO＆NCIPI

9. 发明专利

JP2005079116A Method for manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2005079116A
公开(公告)日：2005-03-24
申请号：JP2003209628
申请日：2003-08-29
申请人： Semiconductor Leading Edge Technologies Inc , 株式会社半導体先端テクノロジーズ
发明人： FURUYA AKIRA , OKAMURA HIROSHI , OTSUKA NOBUYUKI , OGAWA SHINICHI
IPC分类号： H01L21/28 , H01L21/3065 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device for preventing diffusion to the interlayer insulating film of a wiring material, such as a barrier metal and Cu.
SOLUTION: The method for manufacturing the semiconductor device has a process for forming a thin film made of an insulating material on a substrate, a process for opening a hole on the thin film, a process for exposing the thin film to the atmosphere of rare gas plasma, and a process for depositing a conductive material into the hole. In this manner by forming a reformed layer on the surface of the interlayer insulating film, the diffusion to the interlayer insulating film of the barrier metal and the wiring material (Cu) can be prevented reliably and easily.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种制造用于防止扩散到诸如阻挡金属和Cu的布线材料的层间绝缘膜的半导体器件的方法。解决方案：半导体器件的制造方法具有在基板上形成由绝缘材料制成的薄膜的工艺，在薄膜上打开孔的工艺，将薄膜暴露于大气的工艺的稀有气体等离子体，以及用于将导电材料沉积到孔中的工艺。以这种方式，通过在层间绝缘膜的表面上形成重整层，可以可靠且容易地防止对阻挡金属的层间绝缘膜和布线材料（Cu）的扩散。版权所有（C）2005，JPO＆NCIPI

10. 发明专利

JP2005033191A Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2005033191A
公开(公告)日：2005-02-03
申请号：JP2004174410
申请日：2004-06-11
申请人： Semiconductor Leading Edge Technologies Inc , 株式会社半導体先端テクノロジーズ
发明人： OTSUKA NOBUYUKI , FURUYA AKIRA , OGAWA SHINICHI , OKAMURA HIROSHI
IPC分类号： H01L21/3205 , H01L21/768
摘要： PROBLEM TO BE SOLVED: To make it possible to prevent the spread of metal from interconnect lines even in those cases where an insulating film having holes is used.
SOLUTION: In the manufacturing method of the semiconductor device, the insulating film having holes is formed on a lower layer substrate, and an aperture is formed in the insulating film. Then, material gas is provided to the insulating film to supply Si or C. In this way, elements such as Si and C that the insulating film lacks are provided to the insulating film. After that, a wiring structure is formed by embedding a conducting member at least inside the aperture.
COPYRIGHT: (C)2005,JPO&NCIPI

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