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81. 发明专利

JP2007214960A Flip-flop circuit and frequency divider using it 审中-公开
标题翻译： FLIP-FLOP电路和使用它的频率分路器
公开(公告)号：JP2007214960A
公开(公告)日：2007-08-23
申请号：JP2006033595
申请日：2006-02-10
申请人： Oki Electric Ind Co Ltd , 沖電気工業株式会社
发明人： AKAHORI AKIRA
IPC分类号： H03K3/356 , H03K23/00
CPC分类号： H03K23/58 , H03K3/012 , H03K3/356139 , H03K23/60
摘要： PROBLEM TO BE SOLVED: To obtain low power consumption while operation speed is kept unchanged. SOLUTION: In a toggle type flip-flop circuit (TFF), each signal of an output terminal (out) and an inverse output terminal (outb) latched at latch portions 22A, 22B are converted through a clock (ck) and an inverse clock (ckb). A load transistor 21-11 connected to the output terminal (out) is subjected to continuity control by a signal from the inverse output terminal (outb), and a load transistor 21-12 connected to the inverse output terminal (outb) is subjected to continuity control by a signal from the output terminal (out). In this way, the low power consumption is ensured while rising speed of H level signal is kept unchanged. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了在运行速度保持不变的情况下获得低功耗。解决方案：在触发式触发器电路（TFF）中，锁存部分22A，22B上锁存的输出端子（out）和反向输出端子（outb）的每个信号通过时钟（ck）和反时钟（ckb）。连接到输出端子（out）的负载晶体管21-11通过来自反向输出端子（outb）的信号进行导通性控制，连接到反相输出端子（outb）的负载晶体管21-12被通过输出端子（输出）的信号进行连续性控制。这样，在H电平信号的上升速度保持不变的同时确保低功耗。版权所有（C）2007，JPO＆INPIT

82. 发明专利

JP3946077B2 Latch-type level converter and a receiving circuit 有权
公开(公告)号：JP3946077B2
公开(公告)日：2007-07-18
申请号：JP2002122513
申请日：2002-04-24
申请人：富士通株式会社
发明人：慎一郎松尾 , 英規高内
IPC分类号： H03K19/0185 , H03K3/356 , H03K19/0175 , H03M9/00
CPC分类号： H03M9/00 , H03K3/356139

83. 发明专利

JP3872733B2 Method and apparatus for mitigating the history effect in the circuit on silicon (soi) based insulation material 有权
公开(公告)号：JP3872733B2
公开(公告)日：2007-01-24
申请号：JP2002222365
申请日：2002-07-31
申请人：ヒューレット・パッカード・カンパニーHewlett−Packard Company
发明人：フィリップ・エル・バーンズ
IPC分类号： H03K19/0948 , G11C7/06 , G11C7/10 , H03F3/45 , H03K3/356
CPC分类号： G11C7/1087 , G11C7/065 , G11C7/1078 , H03K3/356139 , H03K3/356191
摘要： A method and apparatus for mitigating the hysteresis effect in a sensing circuit used in the evaluation of a property of a system under test. A state monitor circuit is included for detecting the sensing circuit's state upon evaluating the system's property, e.g., a data out signal level. A feedback control generator is provided for generating a control signal operable to transition the sensing circuit's state to a balanced state, wherein the control signal's logic state is capable of being modified substantially immediately upon completion of the evaluation operation.

84. 发明专利

JP2005318609A Differential master/slave cml latch 审中-公开
标题翻译：差异主/从动CML锁
公开(公告)号：JP2005318609A
公开(公告)日：2005-11-10
申请号：JP2005129077
申请日：2005-04-27
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： MELTZER DAVID , PADAPARAMBIL MURALIKUMAR A , TAT C WU
IPC分类号： H03K3/3562 , H03K3/0233 , H03K3/037 , H03K3/356 , H03K5/26 , H03K19/003 , H03L7/089
CPC分类号： H03K3/356139 , H03K3/3562
摘要： PROBLEM TO BE SOLVED: To provide a phase and frequency detector having a differential architecture so that its operation can be performed at the highest possible frequency and with low noise generation. SOLUTION: A fully differential phase and frequency detector utilizes a multi-function differential logic gate to implement a differential AND gate operation and provides a fully differential D-flip-flop. The multi-function differential logic gate has four inputs, which can be grouped into two pairs of true and complement signals. By selectively re-assigning the inputs to different signal pairs, the differential logic gate can be made to provide one of either simultaneous AND/NAND logic operations or simultaneous OR/NOR logic operations. The differential D-flip-flop is implemented following a master/slave configuration and responds to the true and complement forms of an input clock signal, an input reset input, and input data signal, and also provides true and complement forms of an output signal. All elements within the phase and frequency detector are exemplified in CML circuit configuration. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供具有差分架构的相位和频率检测器，使得其可以以最高可能频率执行并且具有低噪声产生。解决方案：全差分相位和频率检测器利用多功能差分逻辑门来实现差分和门操作，并提供全差分D触发器。多功能差分逻辑门有四个输入，可以分为两对真和补两个信号。通过选择性地将输入重新分配给不同的信号对，可以使差分逻辑门提供同时的与/或非逻辑运算或同时的OR / NOR逻辑运算之一。差分D触发器按照主/从配置实现，并响应输入时钟信号，输入复位输入和输入数据信号的真实和补码形式，并提供输出信号的真实和补码形式。相位和频率检测器中的所有元件都以CML电路配置为例。版权所有（C）2006，JPO＆NCIPI

85. 发明专利

JP2005518239A How to manufacture and use of the occlusion device and the occlusion device 审中-公开
公开(公告)号：JP2005518239A
公开(公告)日：2005-06-23
申请号：JP2003570704
申请日：2003-02-18
申请人：インテグレーテツド・バスキユラー・システムズ・インコーポレイテツド
发明人：オールドリツヒ，ウイリアム・エヌ , カーリイ，マイケル・テイ , サガステガイ，ハビエル , ジヤバ，ロナルド・ジエイ , ジン，リチヤード・エス , ベレフ，マーテイン・ダブリユ
IPC分类号： A61B17/08 , A61B17/00 , A61B17/064 , A61B17/068 , A61B17/10 , A61B17/12 , A61B19/00 , H03K3/356
CPC分类号： A61B17/08 , A61B17/0057 , A61B17/064 , A61B17/0644 , A61B17/068 , A61B17/083 , A61B90/39 , A61B2017/00004 , A61B2017/00637 , A61B2017/00668 , A61B2017/00672 , A61B2017/00867 , A61B2017/0641 , A61B2017/081 , H03K3/356139 , H03K3/356156
摘要：組織と係合するクリップは、１つの平面を画定するとともに、この平面と略直交して延びる中心軸を中心に配置された略環状の本体を備えている。本体は、クリップの外周にわたってジグザグパターンを形成する、交互に位置する内側湾曲部位と外側湾曲部位とを有している。本体は、平面内に横たわる平面形態へと付勢されており、平面外に延びる垂直形態へと偏向することができる。内側湾曲部位から歯が延びており、歯は、平面形態においては中心軸に向かって方向付けられ、垂直形態においては中心軸と平行に方向付けられる。歯は、主歯と、主歯よりも短い副歯とを有していても良い。主歯は、対向する内側湾曲部位上に配置されるとともに、平面形態において重なり合うように互いの方に向かって方向付けられていても良い。

86. 发明专利

JP3655505B2 Tri-state buffer circuit 有权
公开(公告)号：JP3655505B2
公开(公告)日：2005-06-02
申请号：JP26267899
申请日：1999-09-16
申请人：株式会社東芝
发明人：田尊吉 , 野勝士平 , 川誠幸早
IPC分类号： H03K19/0175 , H03K3/356 , H03K19/094
CPC分类号： H03K3/356156 , H03K3/356139 , H03K19/09429

87. 发明专利

JP3604628B2 Data receiver 有权
公开(公告)号：JP3604628B2
公开(公告)日：2004-12-22
申请号：JP2000389499
申请日：2000-12-21
申请人：三星電子株式会社
发明人：基煥宋
IPC分类号： G05F3/24 , G11C11/407 , H03K3/012 , H03K3/013 , H03K3/356 , H03K5/08 , H04L25/02 , H04L25/03
CPC分类号： H03K3/013 , H03K3/012 , H03K3/356139

88. 发明专利

JP3556900B2 High-speed dynamic latch 有权
公开(公告)号：JP3556900B2
公开(公告)日：2004-08-25
申请号：JP2000371950
申请日：2000-12-06
申请人：三星電子株式会社
发明人：敏圭宋 , 政垠李 , 啓▲オク▼ 趙
IPC分类号： H03M1/34 , G11C7/00 , H03K3/356 , H03K5/08
CPC分类号： H03K3/356139 , H03K3/356156 , H03K3/356191

89. 发明专利

JP2004234822A Soi sense amplifier 有权
标题翻译： SOI SENSE放大器
公开(公告)号：JP2004234822A
公开(公告)日：2004-08-19
申请号：JP2004001470
申请日：2004-01-06
申请人： Internatl Business Mach Corp , インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation
发明人： AIPPERSPACH ANTHONY GUS
IPC分类号： G11C11/419 , G11C7/06 , H03K3/011 , H03K3/356
CPC分类号： H03K3/356139 , G11C7/065 , H03K3/011
摘要： PROBLEM TO BE SOLVED: To provide a device and a method which reduce fluctuations in the timing delay of the output signal obtained from an SOI technology sense amplifier. SOLUTION: A cross-coupled latch has body-contact FETs 84, 86 whose body is connected to either of a source or a drain and it minimizes switching history effect and in the latch, each of input FETs 80, 82 has a gate switching voltage higher than a regular gate switching voltage and, at the same time, the FETs increase the sensitivity of input signals. COPYRIGHT: (C)2004,JPO&NCIPI

90. 发明专利

JP2003046385A High speed input receiver for generating pulse signal 有权
标题翻译：用于产生脉冲信号的高速输入接收器
公开(公告)号：JP2003046385A
公开(公告)日：2003-02-14
申请号：JP2002074363
申请日：2002-03-18
申请人： Samsung Electronics Co Ltd , 三星電子株式会社
发明人： LEE JONG CHEOL , IN YOSHIN , RI KOSHIN
IPC分类号： G06F3/00 , H03K3/00 , H03K3/012 , H03K3/356 , H03K19/0175
CPC分类号： H03K3/356139 , H03K3/012 , H03K3/356156
摘要： PROBLEM TO BE SOLVED: To provide an input receiver for generating a pulse signal suitably for converting an external signal into a signal of a pulse form by a semiconductor device or the like.
SOLUTION: The input receiver comprises a clock sampled amplifier for receiving a main clock signal and a reference signal, respectively, in response to a first state of the main clock signal and a sampling clock signal delayed from the main clock by a prescribed time, and for amplifying and sampling the voltage difference between the external signal and the reference signal, respectively, in response to a transition of the clock and delayed sampling clock signals to a second state; and a pulse generator that has an output node, is connected between a power supply voltage and a ground voltage, pre-charges the output node to a power source voltage level when the sampling clock is in the first state and pulls down the output node selectively to the level of the ground voltage according to the signal amplified, sampled by the clock sample amplifier and outputted when the sampling clock transits to the second state so as to output a pulse signal.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种用于通过半导体器件等适当地产生用于将外部信号转换成脉冲形式的信号的脉冲信号的输入接收器。解决方案：输入接收机包括响应于主时钟信号的第一状态和从主时钟延迟预定时间的采样时钟信号分别接收主时钟信号和参考信号的时钟采样放大器，以及用于分别响应于时钟的转变和延迟的采样时钟信号而将外部信号和参考信号之间的电压差放大和采样到第二状态; 并且具有连接在电源电压和接地电压之间的输出节点的脉冲发生器，当采样时钟处于第一状态并且选择性地下拉输出节点时，将输出节点预充电到电源电压电平根据放大的信号到接地电压的电平，由时钟采样放大器采样，当采样时钟转换到第二状态时输出，以输出脉冲信号。

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