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71. 发明专利

JPH0327655A EXCHANGE SYSTEM WITH SUBSCRIBER STATE MANAGEMENT FUNCTION 失效
公开(公告)号：JPH0327655A
公开(公告)日：1991-02-06
申请号：JP16226989
申请日：1989-06-23
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： SAKUMA TETSUO , MIZUHARA NOBORU , TSUNODA TOMOAKI , YAMAGISHI JUNKO
IPC分类号： H04M3/42
摘要： PURPOSE:To allow a call to reach a telephone set or the like in the vicinity even when a called telephone set is busy and to realize the service corresponding to subscribers by providing a management table registering the state of idle or busy subscriber and allowing a caller to enter its own ID number. CONSTITUTION:When an ID reception signal including an ID number of a called subscriber and of a caller subscriber exists from the idle state, an exchange controller 2 retrieves a busy flag 8d corresponding to the ID number of the called subscriber relating to a subscriber management table 8. As a result of the retrieval of the busy flag 8d, when the busy state of the called subscriber C is recognized, the controller 2 informs to the caller subscriber A of the busy state. As the result of the analysis as to whether or not a telephone set is busy, when the busy state is recognized, the controller 2 retrieves a neighbour telephone number to a neighbour telephone number table 9. When the neighbour telephone number is recognized by the retrieval, whether or not the telephone set of the telephone number is busy is analyzed. When no busy state is discriminated by the analysis, a call signal is sent to the telephone set of the telephone number and the mode is transited to the call state.

72. 发明专利

JPH033031A COORDINATE INPUT DEVICE 失效
公开(公告)号：JPH033031A
公开(公告)日：1991-01-09
申请号：JP13604189
申请日：1989-05-31
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： AOKI HIDEYUKI , KATO MASAMICHI
IPC分类号： G06F3/153
摘要： PURPOSE:To rapidly change a grid by providing the coordinate input device itself with a grid setting means and a means for correcting an input coordinate value to the coordinate value of the nearest grid. CONSTITUTION:A moving amount detecting mechanism 103 detects the moving amount of the coordinate input device and applies the detected value to an adding register 104, which adds the detected value and stores the added result. Respective storage devices 106 to 110 respectively store the reference point of the grids, the interval between the grids, a current input coordinate value, information relating to the changing method of the grid interval, and the ratio of the input device moving variable to an input coordinate moving variable. Respective control lines 21, 31 are connected to a grid interval changing key and the grid interval changing mechanism 105 changes the grid interval of the storage device 107 in accordance with the grid interval changing method stored in the storage device 109 when the key is depressed. Consequently, a coordinate value inputted by the coordinate input device can be optionally controlled and highly accurately and rapidly inputted.

73. 发明专利

JPH031229A ARITHMETIC UNIT 失效
公开(公告)号：JPH031229A
公开(公告)日：1991-01-07
申请号：JP12794490
申请日：1990-05-17
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： CHIYANDORABEDAN ENU PATERU , RICHIYAADO DABURIYUUEMU BURASU , KIUCHI ATSUSHI , INADA HIROMITSU
IPC分类号： G06F7/38 , G06F7/483 , G06F7/52 , G06F7/523 , G06F7/57 , G06F17/10
摘要： PURPOSE:To support the processing arithmetic operation of a high functional digital signal flexibly for manifold requests by employing a constitution capable of selecting and connecting the input/output of a multiplication means, an arithmetic and logic unit, a barrel shifting means, and a shifting means. CONSTITUTION:The constitution capable of selecting and connecting the input/ output of the multiplication means 2, the arithmetic and logic unit 12, the barrel shifting means 16, and the shifting means 8 and 10 functions so as to support the processing arithmetic operation of the high functional digital signal flexibly for the manifold requests based on control for the connecting state of the input/ output, etc. And it functions so as to support the processing arithmetic operation of a digital signal with high accuracy with a function proper to the individual functional block of the multiplication means 2, etc. In such a manner, it is possible to obtain an arithmetic unit for a digital processor capable of performing the multiplication processing of numbers with codes or without codes, or that of the number with the code and that without the code.

74. 发明专利

JPH02311014A ARBITRATION CIRCUIT 失效
公开(公告)号：JPH02311014A
公开(公告)日：1990-12-26
申请号：JP13138889
申请日：1989-05-26
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： KITAZAWA AKITOSHI
IPC分类号： G06F15/16 , G06F13/362 , G06F15/177 , H03K17/00
摘要： PURPOSE:To reduce a time reaching the circuit equilibrium without reducing the response speed by providing a pulse generating means generating a bow pulse and a detection means for simultaneous change in input signals, applying external disturbance to a feedback path and using an advance generating system. CONSTITUTION:When input signals A, B go simultaneously to an H level, FF outputs Q, inverse of Q of NOR gates 12a, 12b rise simultaneously to keep the equilibrium. In this case, inverters 14a, 14b and a NAND gate 15 generate a one-shot pulse (a). The pule (a) is integrated by an RC circuit to generate a bow pulse (b). When the voltage of a node n2 rises, a MOSFET 4 is turned on, the level of the inverse of Q is at an L and the equilibrium is unbalanced and converged. In such a case, since the potential of the node n1 is always changing timewise, external disturbance exerted to the inverse of Q output changes accordingly. As a result, the circuit acts like unbalancing the equilibrium.

75. 发明专利

JPH02294961A ROTARY HEAD SWITCHING CIRCUIT FOR MAGNETIC RECORDING AND REPRODUCING DEVICE 失效
公开(公告)号：JPH02294961A
公开(公告)日：1990-12-05
申请号：JP11496489
申请日：1989-05-10
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： OKADA YOSHITAKA , ITOIGAWA KEIICHI , TOEDA HIROSHI
IPC分类号： G11B15/14
摘要： PURPOSE:To obtain the stable output of a monostable multivibrator by controlling a time constant circuit, which is composed of resistance and capacity to determine the output pulse width of the monostable multivibrator, according to the output of a phase comparator. CONSTITUTION:A first monostable multivibrator 22 is driven by an up / down edge detector 21 of head switching pulses 1 and 2. A second monostable multivibrator 24 is driven by a down edge outputted from the monostable multivibrator 22. The phase of down edge outputted from the monostable multivibrator 24 is compared 31 with the phase of the edge for the pulses 1 and 2 and a current flows to capacity 29, which determines the prescribed number of the monostable multivibrators 22, so as to eliminate phase difference. Then, a time constant is changed. Thus, the first monostable multivibrator 22 can be made stable without being affected to the change of a temperature characteristic, the change of a power supply voltage and the dispersion of the resistance and capacity.

76. 发明专利

JPH02257733A LOOP TRANSMISSION SYSTEM 失效
公开(公告)号：JPH02257733A
公开(公告)日：1990-10-18
申请号：JP7666289
申请日：1989-03-30
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： NAKAMURA KAZUNORI , SUKEGAWA FUMIO , NAKAYAMA HARUYUKI
IPC分类号： H04L12/42
摘要： PURPOSE:To eliminate the need for the limit of node number due to alignment jitter by devising a system such that the number of node equipments pulling-in a data from a same system in a closed loop by loopback connection does not exceed continuously a prescribed number (n) determined in advance. CONSTITUTION:The system is provided with a reception section 10 receiving a signal from active and reserve system transmission lines, a transmission section 12 sending a signal to the transmission line of the active and reserve system, a control section 13, a SW section 11 applying the selection control of a data and a clock based on an instruction from the control section 13 and an oscillator 14 for internal clock. Plural node equipments 1-6 are connected to the active and reserve system loop transmission lines. Then the system is so devised that the number of node equipments pulling-in the data from a same system does not exceed continuously the prescribed number (n) determined in advance, in a closed loop formed by a loopback connection. Thus, the limit of the node number by alignment jitter is eliminated.

77. 发明专利

JPH02250357A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02250357A
公开(公告)日：1990-10-08
申请号：JP7065689
申请日：1989-03-24
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： KANAI FUMIYUKI , HOTTA KATSUHIKO , ONOZUKA YUKIKO , YOSHIDA MASAYOSHI
IPC分类号： H01L21/768 , H01L21/316
摘要： PURPOSE:To enhance reliability and a yield of a semiconductor device by a method wherein an insulating film is constituted of a borophosphosilicate glass (BPSG) film containing boron and phosphorus and the BPSG film is formed as a laminated structure of a plurality of layers in which concentrations of boron and phosphorus contained in the individual layers are different. CONSTITUTION:A BPSG film 6 is formed of a plurality of layers, e.g. as a three-layer structure; concentrations of boron and phosphorus contained in these layers are increased in the order of lower layer 60, an intermediate layer 61 and an upper layer 62. That is to say, a reflow becomes easier from the lower layer 60 toward the upper layer 62. Accordingly, an overhang is not produced at contact holes 8 in the BPSG film 6 even by the reflow; it is possible to obtain the contact holes 8 of a taper shape; it is possible to prevent a discon nection in an upper-layer wiring part 7. Thereby, it is possible to prevent the overhang, to prevent a disconnection at a connection and to enhance reliability and a yield.

78. 发明专利

JPH02248071A OSCILLATION CIRCUIT 失效
公开(公告)号：JPH02248071A
公开(公告)日：1990-10-03
申请号：JP6772389
申请日：1989-03-22
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： SUZUKAWA KAZUFUMI , SHIMIZU TAKAYOSHI
IPC分类号： H01L27/04 , H01L21/82 , H01L21/822 , H01L27/118 , H03B5/36
摘要： PURPOSE:To reduce noises so as to improve an oscillation circuit in reliability by a method wherein a gate formed of a CMOS is provided between two MOSs in an oscillation circuit in which a feedback resistor is realized through resistance between the drain and the source of a PMOS and an NMOS. CONSTITUTION:As shown in a figure, a PMOS (gate 3a, diffusion layer 2c), a CMOS (gate 3a, diffusion layers 2a and 2b), and an NMOS (gate 3a, diffusion layer 2d) are successively arranged from top to bottom, and wirings 5a (l1) and 5b (l2), which connect them, are arranged in parallel in a longitudinal direction. By this arrangement, the of the wirings 5a and 5b can be made nearly linear and minimized in length, so that noises are prevented from occurring due to wiring made large in length. The wirings 5a and 5b can be made equal in length (l1=l2), so that noises caused by the length difference between wirings can be prevented, and moreover the wiring 5a can be made separate from the wiring 5b by the length of the gate 3a. wherefore crosstalk noises are restrained. By this constitution, an oscillation circuit of this design can be improved in reliability.

79. 发明专利

JPH02232552A HEAT GENERATION OF RESIN SEALED STRUCTURAL BODY AND EVALUATION OF SMOKING VALUE 失效
公开(公告)号：JPH02232552A
公开(公告)日：1990-09-14
申请号：JP5193889
申请日：1989-03-06
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： HAYAKAWA JUNJI , KITANO JUNJIRO
IPC分类号： G01N25/00 , H01L21/56
摘要： PURPOSE:To enable evaluation of a heating yield strength of a resin sealed structural body for an actual part by using both end of a conductive pin as a terminal for a heat generation circuit which energizes a joint to generate heat with a forward bias operation thereof. CONSTITUTION:A conductive pin 3 of a resin sealed structural body 1 is used as a low potential terminal for a heat generation circuit while a conductive pin 4 as high potential terminal and a reverse bias diode Do of a semiconductor chip 5 is forward biased to generate a drop in a forward voltage. With such an arrangement, a resin sealed structural body heat generation circuit is formed to generate heat by consumption of power of impedances Z1 and Z2 and a diode Do and is used to make the structural body 1 generate heat. When a substrate thereof is made of silicon, a chip 5 has a process construction and in any of the construction, a unit element group is separated electrically with a PN isolation so that the highest potential or the lowest potential applied to an electrode of the chip 5 connected to a substrate of the chip 5. Thus, when the PN isolation is forward biased, a drop in the forward voltage of PN junction is obtained to allow the circuit to be used as heat generation circuit.

80. 发明专利

JPH02226355A LOAD BALANCE CONTROL METHOD 失效
公开(公告)号：JPH02226355A
公开(公告)日：1990-09-07
申请号：JP4536989
申请日：1989-02-28
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： YAMAMOTO AKIRA , TSUBOI TOSHIAKI , NANBA TATSUO , KURANO AKIRA , DOI TAKASHI , KITAJIMA HIROYUKI
IPC分类号： G06F13/14
摘要： PURPOSE:To balance an input / output load to each controller by systematically changing an input / output device so that the throughput of the controller or the total sum of availability can be made maximum, and systematically changing the input / output device so as to balance the load of each controller. CONSTITUTION:Two channels A21 and B22 connected to a CPU 20 and controllers A23 and B24 respectively connected to these channels are provided. Further, plural cartridge type MTs 25 commonly connected to these controllers are provided. By using an analysis model, the throughput of a data transferring route, availability and input / output waiting time, etc., are forecasted by computation. As a result, when the MT controlled by the controller of large load quantity is systematically changed under the control of the controller having the small load quantity, the throughput availability and I/O responding time are computed concerning respective cases that the respective MTs are used as the objects of the systematic change. Then, the MT, for which the throughput of the both controllers and availability are most improved by the systematic change, is defined as the object of the move. Thus, the load of each controller can be balanced.

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