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1. 发明专利

JPS58145993A PITCH EXTRACTION OF VOICE 失效
公开(公告)号：JPS58145993A
公开(公告)日：1983-08-31
申请号：JP2749282
申请日：1982-02-24
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： NAKADA KAZUO , INADA HIROMITSU
IPC分类号： G10L25/90

2. 发明专利

JPS58154000A VOICE SYNTHESIZATION SYSTEM 失效
公开(公告)号：JPS58154000A
公开(公告)日：1983-09-13
申请号：JP3644482
申请日：1982-03-10
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： NAKADA KAZUO , HARA HIDEO , INADA HIROMITSU
IPC分类号： G10L19/08

3. 发明专利

JPH02288916A DIGITAL PEAK/VALLEY DETECTING CIRCUIT 失效
公开(公告)号：JPH02288916A
公开(公告)日：1990-11-28
申请号：JP3418990
申请日：1990-02-15
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： CHIYANDORABEDAN ENU PATERU , RICHIYAADO DABURIYUUEMU BURASU , KIUCHI ATSUSHI , INADA HIROMITSU
IPC分类号： G06F7/02 , G01R19/04
摘要： PURPOSE:To detect addresses of a peak value and a valley value by storing value data and its address data in a valley value data storage means and a valley value address storage means respectively at the time when supplied value data is smaller than a valley value. CONSTITUTION:A minimum value and a maximum value are initially set to a peak value data register 18 and a valley value data register 20 respectively, and contents of the peak value data register 18 are successively rewritten with the peak value of value data included in digital data when this digital data including address data and value data is successively supplied. In the same manner, contents of the valley value data register 20 are successively rewritten with the valley value of value data included in the digital data, and the value of a valley value address register 16 is updated to address data corresponding to stored valley value data. Thus, not only the peak value and the valley value but also addresses of the peak value and the valley value are detected.

4. 发明专利

JPH031229A ARITHMETIC UNIT 失效
公开(公告)号：JPH031229A
公开(公告)日：1991-01-07
申请号：JP12794490
申请日：1990-05-17
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： CHIYANDORABEDAN ENU PATERU , RICHIYAADO DABURIYUUEMU BURASU , KIUCHI ATSUSHI , INADA HIROMITSU
IPC分类号： G06F7/38 , G06F7/483 , G06F7/52 , G06F7/523 , G06F7/57 , G06F17/10
摘要： PURPOSE:To support the processing arithmetic operation of a high functional digital signal flexibly for manifold requests by employing a constitution capable of selecting and connecting the input/output of a multiplication means, an arithmetic and logic unit, a barrel shifting means, and a shifting means. CONSTITUTION:The constitution capable of selecting and connecting the input/ output of the multiplication means 2, the arithmetic and logic unit 12, the barrel shifting means 16, and the shifting means 8 and 10 functions so as to support the processing arithmetic operation of the high functional digital signal flexibly for the manifold requests based on control for the connecting state of the input/ output, etc. And it functions so as to support the processing arithmetic operation of a digital signal with high accuracy with a function proper to the individual functional block of the multiplication means 2, etc. In such a manner, it is possible to obtain an arithmetic unit for a digital processor capable of performing the multiplication processing of numbers with codes or without codes, or that of the number with the code and that without the code.

5. 发明专利

JPS58145994A EXTRACTION OF RESIDUAL WAVEFORM 失效
公开(公告)号：JPS58145994A
公开(公告)日：1983-08-31
申请号：JP2749382
申请日：1982-02-24
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： INADA HIROMITSU , NAKADA KAZUO
IPC分类号： G10L19/08

6. 发明专利

JP2003006144A Semiconductor integrated circuit and computer-readable recording medium 审中-公开
标题翻译：半导体集成电路和计算机可读记录介质
公开(公告)号：JP2003006144A
公开(公告)日：2003-01-10
申请号：JP2001192202
申请日：2001-06-26
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YAMATO TETSUYA , INADA HIROMITSU , MATSUDA KEISUKE , TAKADA KAZUYUKI , UTO AKIHIRO
IPC分类号： G06F12/02 , G06F3/06 , G06F12/04 , G06F13/00 , G06F13/36 , G06F13/38 , H04L12/70 , H04L12/56
CPC分类号： G06F3/0613 , G06F3/0661 , G06F3/0677
摘要： PROBLEM TO BE SOLVED: To realize data structure conversion between a serial packet and a parallel packet, without causing increase in the load of a CPU.
SOLUTION: A protocol conversion part (24) flexibly maps a plurality of different function areas into an area (25) for protocol conversion of a memory (5) according to a set value of a register part (33) for mapping, with respect to a storage area for different pieces of function information constituting a serial packet, allocates needed information to the plurality of different function areas and performs serial packet conversion, that is, converts interface protocol of the serial packet into an interface packet of a parallel packet. Since information of different data structure can be flexibly stored on the memory 5 managed with the so-called UMA(unified memory architecture) system, it is possible to realize high-speed data structure conversion, without being affected by the limitation of a memory access boundary or imposing a large load on a CPU.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：实现串行数据包和并行数据包之间的数据结构转换，而不会增加CPU的负载。解决方案：协议转换部分（24）根据用于映射的寄存器部分（33）的设置值将多个不同的功能区域灵活地映射到用于协议转换存储器（5）的区域（25）中，相对于用于构成串行分组的不同功能信息的存储区域，将所需信息分配给多个不同的功能区域，并进行串行分组转换，即将串行分组的接口协议转换为并行分组的接口分组。由于不同数据结构的信息可以灵活地存储在由所谓的UMA（统一存储器架构）系统管理的存储器5中，所以可以不受存储器访问限制的影响而实现高速数据结构转换边界或在CPU上施加大量负载。

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