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61. 发明专利

JP3993717B2 Semiconductor integrated circuit device 有权
公开(公告)号：JP3993717B2
公开(公告)日：2007-10-17
申请号：JP16133199
申请日：1999-06-08
申请人：富士通株式会社
发明人：靖治佐藤 , 浩由富田 , 康郎松崎 , 和一郎藤枝 , 暢孝谷口
IPC分类号： G11C11/407 , G11C11/4076 , G06F1/08 , G06F1/10 , G11C7/10 , G11C7/22 , G11C11/406 , H03K5/13 , H03K5/135 , H03K23/58 , H03L7/00 , H03L7/081
CPC分类号： H03L7/0805 , G06F1/08 , G06F1/10 , G11C7/1039 , G11C7/1045 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , H03K5/133 , H03K23/58 , H03L7/0814

62. 发明专利

JP2007259150A Delay control circuit 有权
标题翻译：延时控制电路
公开(公告)号：JP2007259150A
公开(公告)日：2007-10-04
申请号：JP2006081698
申请日：2006-03-23
申请人： Fujitsu Ltd , 富士通株式会社
发明人： ARIYOSHI KATSUHIKO , SETSU SOYO , OBARA RYUSUKE
IPC分类号： H03K5/135 , H03K5/131
CPC分类号： H03L7/0805 , H03K5/133 , H03K2005/00065 , H03K2005/00071 , H03L7/0814 , H03L7/089
摘要： PROBLEM TO BE SOLVED: To provide a delay control circuit having a small area and capable of keeping constant accuracy with low power consumption. SOLUTION: In a first variable delay means 101, first delay is given to a first edge of an input signal by delaying the input signal so as to generate a first delay signal. In a second variable delay means 102, second delay is given to a second edge of an input signal by delaying the input signal so as to generate a second delay signal. The first variable delay means 101 and the second variable delay means 102 are so controlled by a control means 103 that the first delay and the second delay are in agreement. In a generating means 104, the first edge of the first delay signal and the second edge of the second delay signal are combined so that a third delay signal is generated. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有小面积并能够以低功耗保持恒定精度的延迟控制电路。解决方案：在第一可变延迟装置101中，通过延迟输入信号来给输入信号的第一边缘提供第一延迟，以产生第一延迟信号。在第二可变延迟装置102中，通过延迟输入信号以产生第二延迟信号，给输入信号的第二边沿提供第二延迟。第一可变延迟装置101和第二可变延迟装置102由控制装置103控制，第一延迟和第二延迟一致。在发生装置104中，组合第一延迟信号的第一边缘和第二延迟信号的第二边缘，从而产生第三延迟信号。版权所有（C）2008，JPO＆INPIT

63. 发明专利

JP2007208774A Phase control circuit 审中-公开
标题翻译：相控电路
公开(公告)号：JP2007208774A
公开(公告)日：2007-08-16
申请号：JP2006026667
申请日：2006-02-03
申请人： Yokogawa Electric Corp , 横河電機株式会社
发明人： UCHIDA KENJI , MIURA AKIRA , ODAKA HIROHISA , YAGIHARA TAKESHI , TANIMURA DAISUKE , TEZUKA KENTARO , BUTATSU KENTARO
IPC分类号： H03K5/26 , H03K5/135 , H03L7/00
CPC分类号： H03L7/0812 , H03L7/091 , H04L7/0037 , H04L7/033
摘要： PROBLEM TO BE SOLVED: To attain a phase control circuit by which optimal timing adjustment is always performed irrespective of aging and a temperature variation. SOLUTION: The phase control circuit which controls phases has: a variable delay circuit which delays a clock signal; a first flip-flop circuit in the clock input terminal of which the delayed clock signal is inputted and in the data input terminal of which a data signal is inputted; a second flip-flop circuit in the clock input terminal of which the data signal is inputted and in the data input terminal of which the delayed clock signal is inputted and an integration circuit which controls a delay amount of the variable delay circuit based on an output signal of the second flip-flop circuit. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了获得无论老化和温度变化如何，始终执行最佳定时调整的相位控制电路。控制相位的相位控制电路具有延迟时钟信号的可变延迟电路; 时钟输入端中输入延迟的时钟信号的第一触发器电路和输入数据信号的数据输入端; 输入数据信号的时钟输入端的第二触发器电路和输入延迟的时钟信号的数据输入端以及基于输出控制可变延迟电路的延迟量的积分电路第二触发器电路的信号。版权所有（C）2007，JPO＆INPIT

64. 发明专利

JP3960267B2 The A / d-conversion method and device 有权
公开(公告)号：JP3960267B2
公开(公告)日：2007-08-15
申请号：JP2003153107
申请日：2003-05-29
申请人：株式会社デンソー
发明人：鉱二安積 , 秀俊山内 , 高元渡辺 , 孝行鳥越
IPC分类号： H03K5/135 , H03M1/60 , H03M1/12 , H03M1/20 , H03M1/50
CPC分类号： H03M1/206 , G04F10/005 , H03M1/502

65. 发明专利

JP3937686B2 Counter compensation method in the ripple counter, and the ripple counter 有权
公开(公告)号：JP3937686B2
公开(公告)日：2007-06-27
申请号：JP2000127910
申请日：2000-04-27
申请人：横河電機株式会社
发明人：明堀田
IPC分类号： H03K5/135 , H03K23/40

66. 发明专利

JP2007150497A Electronic circuit and control method thereof 审中-公开
标题翻译：电子电路及其控制方法
公开(公告)号：JP2007150497A
公开(公告)日：2007-06-14
申请号：JP2005339773
申请日：2005-11-25
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： MINAMIMOTO TAKASHI
IPC分类号： H03K5/00 , H03K5/135
摘要： PROBLEM TO BE SOLVED: To provide an electronic circuit stably operated at a high speed in response flexibly to a change in an operating environment wherein a delay time of a delay circuit for outputting an operation end signal of a combination circuit can properly be changed.
SOLUTION: The electronic circuit includes: the combination circuit for receiving data and an operation start signal and outputting data corresponding to the received data; the delay circuit for receiving a control signal, producing a delay time in response to the control signal, and outputting the operation end signal for informing an external device that the output data from the combination circuit are stabilized; and a control circuit for receiving a reset signal and outputting the control signal of the delay circuit, and when the control circuit receives the reset signal, the control circuit searches delay times for the delay circuit whereby the output data of the combination circuit can stably be captured and controls the control signal to produce the shortest delay time among the delay times.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供稳定地高速运行的电子电路，灵活地响应于操作环境的改变，其中用于输出组合电路的操作结束信号的延迟电路的延迟时间可以适当地改变。电子电路包括：用于接收数据的组合电路和操作开始信号，并输出与接收到的数据相对应的数据; 用于接收控制信号的延迟电路，产生响应于控制信号的延迟时间，并输出用于通知外部设备的来自组合电路的输出数据稳定的操作结束信号; 以及用于接收复位信号并输出延迟电路的控制信号的控制电路，并且当控制电路接收到复位信号时，控制电路检索延迟电路的延迟时间，由此组合电路的输出数据可以稳定地捕获并控制控制信号以在延迟时间之间产生最短的延迟时间。版权所有（C）2007，JPO＆INPIT

67. 发明专利

JP2007122807A Semiconductor storage device and its adjustment method 审中-公开
标题翻译：半导体存储器件及其调整方法
公开(公告)号：JP2007122807A
公开(公告)日：2007-05-17
申请号：JP2005313387
申请日：2005-10-27
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： NISHIOKA NAOHISA , FUJISAWA HIROKI
IPC分类号： G11C11/401 , G11C29/12 , H03K5/135
CPC分类号： G11C7/22 , G11C7/222 , G11C17/16 , G11C17/18
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of adjusting timing of an internal signal, while surely acquiring data written in anti-fuse in initial setting, and its adjustment method.
SOLUTION: Using a reset signal supplied asynchronously with a clock, a DLLReset signal, which is the signal for making the data written in the anti-fuse output, is generated. The DLLReset signal is supplied, each of the anti-fuse block equipped with a plurality of the anti fuses in which the data, required for timing adjustment for the internal signal, is written.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够调整内部信号的定时的半导体存储装置，同时可靠地获取在初始设定中写入反熔丝的数据及其调整方法。
解决方案：使用与时钟异步提供的复位信号，产生一个DLLReset信号，它是将数据写入反熔丝输出的信号。提供DLLReset信号，每个反熔丝块配备有多个反熔丝，其中写入了用于内部信号的定时调整所需的数据。版权所有（C）2007，JPO＆INPIT

68. 发明专利

JP3901297B2 Dll circuit and semiconductor memory device using the same 失效
公开(公告)号：JP3901297B2
公开(公告)日：2007-04-04
申请号：JP24371497
申请日：1997-09-09
申请人：富士通株式会社
发明人：浩由富田
IPC分类号： G11C11/407 , G11C11/417 , G06F1/10 , G11C7/00 , G11C7/22 , G11C11/4076 , H03K5/13 , H03K5/135 , H03L7/00 , H03L7/081
CPC分类号： H03L7/0805 , G11C7/22 , H03K5/131 , H03K5/135 , H03L7/0814 , Y10S331/02

69. 发明专利

JP2007060669A Pulse generator, optical disk writer and tuner 审中-公开
标题翻译：脉冲发生器，光盘写波器和调谐器
公开(公告)号：JP2007060669A
公开(公告)日：2007-03-08
申请号：JP2006226457
申请日：2006-08-23
申请人： Intel Corp , インテルコーポレイション
发明人： SAWYER DAVID ALBERT , COWLEY NICHOLAS PAUL , ALI ISAAC
IPC分类号： H03K5/13 , G11B20/10 , H03K5/00 , H03K5/04 , H03K5/135 , H03K5/15 , H03K5/156 , H03L7/081 , H03L7/18 , H04B1/26
CPC分类号： H03K5/135 , H03K5/133 , H03K5/15 , H03K5/1565 , H03K2005/00286 , H03L7/18
摘要： PROBLEM TO BE SOLVED: To provide a pulse generator capable of enhancing phase balancing or the like of a frequency converter. SOLUTION: The pulse generator comprises an oscillator 3 and a selecting arrangement for selecting how many of a first group 13 of delay elements are connected in series for delaying an IF clock of the pulse generator. Identical delay elements 26 receiving the IF clock in inputs are connected in series to form a second group. A measuring circuit 27 repeatedly measures the delay provided by the second group, for example providing output pulses IP whose pulse width IPD is equal to the delay. Reference pulse generators 29, 30 generate a series of reference pulses RP, each of which has a duration equal with a fraction of the IF clock period. A charge pump/integrator 28 compares the measurement and reference pulses to generate an error signal that is fed back to timing delay control inputs of all the delay elements such that the widths of the measurement and reference pulses are made equal to each other. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供能够增强变频器的相位平衡等的脉冲发生器。解决方案：脉冲发生器包括振荡器3和选择装置，用于选择延迟元件的第一组13中有多少串联连接以延迟脉冲发生器的IF时钟。在输入中接收IF时钟的相同延迟元件26串联连接以形成第二组。测量电路27重复测量由第二组提供的延迟，例如提供脉冲宽度IPD等于延迟的输出脉冲IP。参考脉冲发生器29,30产生一系列参考脉冲RP，每个参考脉冲具有等于IF时钟周期的一部分的持续时间。电荷泵/积分器28比较测量和参考脉冲以产生反馈到所有延迟元件的定时延迟控制输入的误差信号，使得测量和参考脉冲的宽度彼此相等。版权所有（C）2007，JPO＆INPIT

70. 发明专利

JP2006527569A 审中-公开
公开(公告)号：JP2006527569A
公开(公告)日：2006-11-30
申请号：JP2006516663
申请日：2004-06-08
IPC分类号： H03K5/135 , H03K3/03 , H03K5/00 , H03K5/13 , H03K7/08 , H03L7/081

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