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1. 发明专利

JP2007259150A Delay control circuit 有权
标题翻译：延时控制电路
公开(公告)号：JP2007259150A
公开(公告)日：2007-10-04
申请号：JP2006081698
申请日：2006-03-23
申请人： Fujitsu Ltd , 富士通株式会社
发明人： ARIYOSHI KATSUHIKO , SETSU SOYO , OBARA RYUSUKE
IPC分类号： H03K5/135 , H03K5/131
CPC分类号： H03L7/0805 , H03K5/133 , H03K2005/00065 , H03K2005/00071 , H03L7/0814 , H03L7/089
摘要： PROBLEM TO BE SOLVED: To provide a delay control circuit having a small area and capable of keeping constant accuracy with low power consumption. SOLUTION: In a first variable delay means 101, first delay is given to a first edge of an input signal by delaying the input signal so as to generate a first delay signal. In a second variable delay means 102, second delay is given to a second edge of an input signal by delaying the input signal so as to generate a second delay signal. The first variable delay means 101 and the second variable delay means 102 are so controlled by a control means 103 that the first delay and the second delay are in agreement. In a generating means 104, the first edge of the first delay signal and the second edge of the second delay signal are combined so that a third delay signal is generated. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有小面积并能够以低功耗保持恒定精度的延迟控制电路。解决方案：在第一可变延迟装置101中，通过延迟输入信号来给输入信号的第一边缘提供第一延迟，以产生第一延迟信号。在第二可变延迟装置102中，通过延迟输入信号以产生第二延迟信号，给输入信号的第二边沿提供第二延迟。第一可变延迟装置101和第二可变延迟装置102由控制装置103控制，第一延迟和第二延迟一致。在发生装置104中，组合第一延迟信号的第一边缘和第二延迟信号的第二边缘，从而产生第三延迟信号。版权所有（C）2008，JPO＆INPIT

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