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51. 发明专利

JP2002093158A SEMICONDUCTOR DEVICE AND MEMORY SYSTEM 失效
公开(公告)号：JP2002093158A
公开(公告)日：2002-03-29
申请号：JP2000278666
申请日：2000-09-08
申请人： HITACHI LTD
发明人： SAKATA TAKESHI , MATSUOKA HIDEYUKI , HANZAWA SATORU
IPC分类号： G11C11/38
摘要： PROBLEM TO BE SOLVED: To provide a memory in which a through current at the time of standby is reduced, integration density is high, and power consumption is low. SOLUTION: Input data DI are encoded by a data encoder LWC to obtain write-data GI, and read-data GO are decoded by a data decoder LWD to obtain output data DO.

52. 发明专利

JP2001068632A SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURE 失效
公开(公告)号：JP2001068632A
公开(公告)日：2001-03-16
申请号：JP23898199
申请日：1999-08-25
申请人： MITSUBISHI ELECTRIC CORP
发明人： MORIMOTO RUI
IPC分类号： G11C11/38 , H01L21/8244 , H01L27/10 , H01L27/11 , H01L29/88
摘要： PROBLEM TO BE SOLVED: To reduce the area of a memory cell in a semiconductor storage device by a method wherein the negative resistance part of the device has tunnel insulating films formed on relatively high-impurity concentration P-type active regions, and an N-type polysilicon film is formed on the tunnel insulating film. SOLUTION: An N-type well 18 is formed on a P-type silicon substrate 21 and P-type active regions 17a and 17b are formed on the well 18. A first interlayer insulating film 19 is formed on these regions 17a and 17b, contact apertures are provided in the film 19 and a BDC(bit line direct control) 4, and an SNDC(storage node direct contact) 8 and a GDC (ground direct contact) 10 are respectively buried in these contact apertures. At this time, tunnel insulating film 4t, 8t and 10t are respectively formed on the regions 17a and 17b in the state corresponding to each of the contacts 4, 8 and 10, and P-type polysilicon films 3 and 6 and an N-type polysilicon film 9 are respectively formed on those films 4t, 8t and 10t.

53. 发明专利

JP2986057B2 失效
公开(公告)号：JP2986057B2
公开(公告)日：1999-12-06
申请号：JP3399895
申请日：1995-02-22
申请人： INTAANASHONARU BIJINESU MASHIINZU CORP
发明人： KATAYAMA YASUNAO
IPC分类号： G11C11/34 , G11C11/38 , H01L27/10 , H01L29/06

54. 发明专利

JPH11186538A PHASE SYNCHRONIZING CIRCUIT DEVICE USING SINGLE ELECTRON TUNNEL JUNCTION ELEMENT AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH11186538A
公开(公告)日：1999-07-09
申请号：JP35570397
申请日：1997-12-24
申请人： FUJITSU LTD
发明人： OSHIMA TOSHIO
IPC分类号： G11C11/38 , G11C13/00 , H01L27/10 , H01L29/66 , H01L45/00 , H01L49/00 , H03K19/08
摘要： PROBLEM TO BE SOLVED: To provide a new composition of a phase synchronizing circuit device using a single electron tunnel junction element and a method of manufacturing the same. SOLUTION: A compact phase synchronizing circuit is formed by composing a load resistor with a tunnel junction device 12 and laminating a single electron tunnel junction 10 and a tunnel junction element 12 for resistor. The load resistor 12 is constituted of a plurality of laminated tunnel junctions 121 to 124 for resistors to provide an appropriate resistance to itself. A direct-current bias voltage Vdc is applied to an electrode 37 of the tunnel junction for resistor and an alternating pump voltage Vpump is applied to an electrode 20 of the single electron tunnel junction element. When forming the phase synchronizing circuit with a plurality of gates, alternating pump voltage is applied to one electrode of the single electron tunnel junction elements which is made common, and the other electrodes are separately formed in planar form. The compact phase synchronizing circuit with the plurality of gates can be formed on the other electrodes by laminating the tunnel junction for resistor.

55. 发明专利

JPH10189888A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH10189888A
公开(公告)日：1998-07-21
申请号：JP28006697
申请日：1997-10-14
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MORITA KIYOYUKI , MORIMOTO TADASHI , YUKI KOICHIRO , ARAKI SEI
IPC分类号： G11C11/38 , H01L27/08 , H01L27/10 , H01L29/88
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having various functions such as a bistable memory, a logic circuit and others by a method, wherein a MIS- type semiconductor element, a resonance tunnel diode, a hot electron transistor and the like are formed on a common substrate. SOLUTION: An N-type Si layer 103a and a P-type Si layer 105 surrounded with an element isolating oxide film 104 are formed on an SOI substrate. A mask oxide film 106a and a gate oxide film 106b are formed, the N-type Si layer 103a is crystal-anisotropically etched using the mask oxide film 106a as a mask, whereby the N-type Si layer 103a is made into a thin Si plate. A tunnel oxide film 107 is formed on each side of the N-type Si layer 103a, the two polysilicon electrodes 109a and 109b formed of a common polysilicon film for a resonant tunnel diode and a polysilicon electorde 109c, which serves as a gate electrode of a MIS semiconductor device, are formed. By this setup, an Si/SiO2 -based quantum device can be manufactured easily at a low cost.

56. 发明专利

JPH10172278A TWO-PORT MEMORY CELL 失效
公开(公告)号：JPH10172278A
公开(公告)日：1998-06-26
申请号：JP32350897
申请日：1997-11-25
申请人： TEXAS INSTRUMENTS INC
发明人： BLAKE TERENCE G W , VAN DER WAGT JAN P
IPC分类号： G11C11/41 , G11C8/16 , G11C11/38 , G11C11/401 , G11C11/405
摘要： PROBLEM TO BE SOLVED: To provide a memory cell with the functionality of a two-port SRAM and a cell density that is close to that of a DRAM. SOLUTION: A two-port memory cell includes a bistable latch made of two resonance tunnel diodes(RTD) 34 and 38 that are connected in series between a supply voltage (+Pwr) and a reference voltage (-Pwr) and the common node 36 of the RTD is connected to both functions of reading and writing of a cell. The writing function is achieved by a field effect pulse transistor 30 that is connected between the node 36 and a bit-writing bus WB and a gate 26 is connected to a word writing bus WW. The reading function is achieved by a sense amplifier n channel transistor 46, a source 44, a gate 40, and a drain 42 are connected to a negative power supply, the node 36, and a power supply 48 of an n-channel path transistor 53, respectively, the transistor 53 depends on the voltage of a gate 50 that is connected to a word-reading line RW, and the drain 42 is connected to a bit-reading line RB.

57. 发明专利

JPH1069766A MEMORY CELL 失效
公开(公告)号：JPH1069766A
公开(公告)日：1998-03-10
申请号：JP21111197
申请日：1997-07-01
申请人： TEXAS INSTRUMENTS INC
发明人： VAN DER WAGT JAN P
IPC分类号： G11C11/38 , G11C11/36
摘要： PROBLEM TO BE SOLVED: To provide a memory cell which has a negative differential resistance device such as a resonance tunneling diode, etc. SOLUTION: The memory cell is composed from a matrix which includes a memory cell on each crossing point between a bit line and a read/write word line. Each memory cell is provided with a first FET 20 whose gate and drain are respectively connected to a write word line and a bit line, a second FET 22 whose source and drain are respectively connected to a bit line and a read word line, and first and second negative resistance devices 24, 26 serially connected between the power source voltage and the substrate voltage. The common point SN of the serially connected negative resistance devices is connected to the source of the first FET 20 and the gate of the second FET 22.

58. 发明专利

JPH09162394A TUNNEL TRANSISTOR AND STORAGE CIRCUIT 失效
公开(公告)号：JPH09162394A
公开(公告)日：1997-06-20
申请号：JP32020095
申请日：1995-12-08
申请人： NEC CORP
发明人： BABA TOSHIO
IPC分类号： G11C11/38 , G11C11/56 , H01L29/78 , H01L29/80
摘要： PROBLEM TO BE SOLVED: To provide a tunnel transistor which has a plurality of negative resistance characteristics by providing a source electrode, a drain electrode and a gate electrode to be formed on a source, a drain and an insulation layer. SOLUTION: When a positive voltage is applied to a drain electrode 8, three n -p tunnel junctions in all between each left edge of P -GaAs connecting areas 9 and the left edge of a P -GaAs drain 3 and channel layers 4 are permitted to be the forward-direction bias wherein negative resistance appears. Two n -p tunnel junctions between the right edge of the p -GaAs connecting areas 9 and the channel layers 4 are permitted to be reverse-direction bias which has low resistance characteristics. Thus, among the n -P tunnel junctions, three tunnel junctions are forward-direction bias, and the two tunnel junctions are reverse-direction bias. Since reverse-direction bias tunnel junction has extremely low resistance compared with forward-direction bias tunnel junction, current between the source 2 and the drain 3 is decided by the tunnel junction characteristics of the high resistance forward-direction bias, and three negative resistance characteristics are permitted to continuously appear.

59. 发明专利

JPH07202139A SWITCHING ELEMENT 失效
公开(公告)号：JPH07202139A
公开(公告)日：1995-08-04
申请号：JP31843294
申请日：1994-12-21
申请人： PHILIPS ELECTRONICS NV
发明人： RONARUDO MARUCHIN UORUFU , PAURUSU UIRUHERUMUSU MARIA BUR , MARUSERINUSU PETORASU KARORUSU
IPC分类号： G11C11/22 , G11C11/38 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/115 , H01L27/11502 , H01L29/47 , H01L29/788 , H01L29/792 , H01L29/872 , H01L29/88 , H01L49/00
摘要： PURPOSE: To provide a switching element having a semiconductor dielectric capable of holding switched state approximately indefinitely. CONSTITUTION: A switching element has two electrodes 1, 2, and a semiconducting dielectric 3 put between them. One electrode 2 has a material for forming a Schottky contact with the dielectric 3, and the space-charge region 3' of this Schottky contact forms a tunneling barrier with respect to electrons during operation. The dielectric 3 is provided with a ferroelectric substance having residual polarization, which affect the magnitude of the tunneling barrier.

60. 发明专利

JPH07111082A ELECTRONIC CIRCUIT 失效
公开(公告)号：JPH07111082A
公开(公告)日：1995-04-25
申请号：JP25688993
申请日：1993-10-14
申请人： NIPPON DENSO CO
发明人： KATO AKIRA , TSUZUKI GENICHI , KATADA MITSUTAKA
IPC分类号： G11C11/38 , H01L29/66
摘要： PURPOSE:To provide an electronic circuit having an information storage function. CONSTITUTION:In a single electronic switch 70 in which capacitors 3, 4 are connected respectively to one side of single electronic tunnel junction transistors 1, 2, a potential holding circuit 72 is connected between an electrode 15 and an 16 of this single electronic switch 70. This potential holding circuit 72 is constituted of a single electronic switch 71 in which capacitors 7, 8 are connected respectively to one end of single electronic tunnel junction transistors 5, 6 and capacitors 9, 10.

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