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    • 1. 发明专利
    • TUNNEL TRANSISTOR AND ITS MANUFACTURE
    • JP2000174256A
    • 2000-06-23
    • JP34132198
    • 1998-12-01
    • NEC CORP
    • ZEN YOSHINBABA TOSHIO
    • H01L29/66H01L29/78
    • PROBLEM TO BE SOLVED: To provide a tunnel transistor having less gate leakage or gate capacity by eliminating a joint area between a gate layer and a source area as well as a joint area between the gate layer and a drain area. SOLUTION: In this tunnel transistor, a channel layer 2 is formed between a source area 5 and a drain area 6, and a gate layer 4 is formed on the channel layer 2 with an insulation layer 3 in between. The tunnel transistor is provided with the first conductivity type channel layer 2 formed on a substrate 1, the insulation layer 3 formed thereon, the gate layer 4 which has second conductivity type different from the first conductivity type and is made of a degenerated semiconductor and is formed on the insulation layer 3, the drain area 6 which is formed on the substrate 1 while being in contact with one side 2a of the channel layer 2 and is made of second conductivity type degenerated semiconductor, the source area 5 which is formed on the substrate 1 while being in contact with the other side 2b of the channel layer 2 and is made of second conductivity type degenerated semiconductor, and a source electrode 7, a gate electrode 8 and a drain electrode 9 which are formed respectively in the source area 5, gate layer 4 and drain area 6.
    • 5. 发明专利
    • FIELD-EFFECT TRANSISTOR
    • JPH03129835A
    • 1991-06-03
    • JP26877489
    • 1989-10-16
    • NEC CORP
    • BABA TOSHIO
    • H01L29/78H01L21/338H01L29/778H01L29/812
    • PURPOSE:To make possible an increase in integration and a high-speed operation by a method wherein a channel layer at a transistor periphery part under a gate electrode is all depleted including the transistor periphery part. CONSTITUTION:A device isolation layer 9, which has a conductivity type different from that of a channel layer 3 and the layer 3 directly under which is completely depleted, is provided on the layer 3, in which carriers travel, and the layer 9 is formed in such a way as to encircle the periphery of a device region consisting of at least source and drain electrodes 6 and 7 and the channel layer. As a result, the fact that a current flows through this region is eliminated and with a leakage current eliminated, this region is completely isolated from other transistor. Thereby, an increase in integration is facilitated and a high- speed operation can be realized applying effectively the characteristics of materials.
    • 6. 发明专利
    • BISTABLE LIGHT EMITTING DEVICE
    • JPH02252283A
    • 1990-10-11
    • JP7469289
    • 1989-03-27
    • NEC CORP
    • BABA TOSHIO
    • G02F3/02H01L33/04H01L33/30H01L33/40H01S5/00H01S5/026H01S5/042
    • PURPOSE:To enable the high performance design and the high integration to be realized by a method wherein a resonance tunnel diode in asymmetrical structure is formed in a light emitting part so as to perform the bistable operations. CONSTITUTION:A resonance tunnel diode in an asymmetrical structure is formed between an emitter layer 8 and a base layer 12 while a laser diode is formed between an n type layer 3 and a p type clad layer 5. When the space between an anode electrode 7 and a cathode electrode 6 is impressed with proper voltage assuming the laser diode structure as a load series-connected to the resonance tunnel diode, two stabilized points in the high current state with high light emission and the low current state with low light emission exist in the voltage current characteristics. Furthermore, when a base electrode 13 is impressed with a specific pulse voltage, the two states in different intensities of light are brought about. Through these procedures, the bistable operation is realized so that the title light emitting device capable of selecting the light emitting wavelength and facilitating the enhanced performance and the high integration may be manufactured.
    • 7. 发明专利
    • SEMICONDUCTOR DEVICE
    • JPH029173A
    • 1990-01-12
    • JP15810988
    • 1988-06-28
    • NEC CORP
    • BABA TOSHIO
    • H01L29/68H01L29/205
    • PURPOSE:To perform operation at a condition where a large current flows and obtain a high current gain, and then perform superhigh-speed operation by injecting electrons from an emitter to a base at a condition of thermal excitation and make the electrons injected into a base layer travel to the second conduction band. CONSTITUTION:Once voltage is impressed between emitter and base layers, depletion layers decrease and a barrier to electrons becomes low, as a result, the injection of the electrons is excited thermally and all the electrons having energy which is higher than that of the barrier are injected from the emitter layer 14 to the base layer 13. In such a case, the electrons are not injected into the first conduction band of the base layer 13 because of difference in symmetry property of the conduction band and are injected into the second conduction band. The electrons obtain energy because of difference in energy of the second conduction band between the emitter and base layers and become hot ones and then, most of them reach a collector barrier layer 12 after passing through the base layer 13. The electrons which are injected into the second conduction band in this way makes this device perform operation at a condition where a large current flows and obtain a high current gain and, then, perform superhigh-speed operation.
    • 8. 发明专利
    • MANUFACTURE OF SEMICONDUCTOR DEVICE
    • JPS62271465A
    • 1987-11-25
    • JP11376186
    • 1986-05-20
    • NEC CORP
    • BABA TOSHIOMIZUTANI TAKASHI
    • H01L29/73H01L21/331H01L29/20H01L29/72H01L29/737
    • PURPOSE: To reduce parasitic capacitance, and to obtain an element capable of being operated at ultra-high speed by burying a collector region into an insulating film so that one part is exposed to the surface and forming a base region to an exposed surface and one part of the surface of the insulating film. CONSTITUTION:An N-type GaAs collector layer 2 is grown on a GaAs substrate 1 in approximately 5000Angstrom , and sections except a transistor element region are etched in approximately 1mum and sections except a transistor operating region in approximately 2000Angstrom respectively. An insulating film 9 is shaped so that the surface of the layer 2 is changed into an exposed flat surface. A P-type GaAs base layer 3 and an N-type emitter layer 4 are grown through a molecular-beam epitaxial method, and sections except an operating region and an electrode region in the base layer 3 are removed through etching. One part of the film 9 is shaved to expose the layer 2, and a collector electrode 6, a base electrode 7 and an emitter electrode 8 are formed.
    • 9. 发明专利
    • Semiconductor device
    • 半导体器件
    • JPS59149063A
    • 1984-08-25
    • JP2393283
    • 1983-02-16
    • Nec Corp
    • BABA TOSHIO
    • H01L29/812H01L21/331H01L21/338H01L29/73H01L29/778H01L29/80
    • H01L29/80
    • PURPOSE:To obtain a semiconductor device, which can apply high forward voltage to a gate and can be operated at high speed, by forming a semiconductor layer, which contains a P type impurity in high concentration and is changed completely into a depletion layer, between a semiconductor layer containing an N type impurity and a gate electrode in an FET utilizing a modulation doping. CONSTITUTION:The titled semiconductor device is constituted by a semi-insulating semiconductor substrate 1, a first semiconductor layer 2 in extremely low impurity concentration, a second semiconductor layer 3 containing an N type impurity, electron affinity thereof is smaller than the first semiconductor layer 2, a third semiconductor layer 7, which contains a P type impurity and is changed completely into a depletion layer, a gate electrode 5 forming a Schottky junction together with the third semiconductor layer 7, and a pair of source and drain electrodes 6, 6' forming electric contacts together with carriers existing on the interface between the first semiconductor layer and the second semiconductor layer. When the P semiconductor layer, which is changed completely into the depletion layer and contains the P type impurity in high concentration, exists between the N type semiconductor layer and a metal, a barrier becomes higher than a Schottky barrier formed by the N type semiconductor and the metal.
    • 目的:为了获得能够向栅极施加高正向电压并且可以高速运行的半导体器件,通过形成包含高浓度的P型杂质并完全改变为耗尽层的半导体层,在 利用调制掺杂的FET中含有N型杂质的半导体层和栅电极。 标题:标题半导体器件由半绝缘半导体衬底1,杂质浓度极低的第一半导体层2,含有N型杂质的第二半导体层3,其电子亲和性小于第一半导体层2 ,包含P型杂质并完全改变为耗尽层的第三半导体层7,与第三半导体层7一起形成肖特基结的栅电极5和一对源电极和漏电极6,6' 与存在于第一半导体层和第二半导体层之间的界面上的载流子一起形成电触头。 当在N型半导体层和金属之间存在完全改变为耗尽层且含有高浓度的P型杂质的P +半导体层时,势垒变得高于由N形成的肖特基势垒 型半导体和金属。
    • 10. 发明专利
    • Manufacture of semiconductor device
    • 半导体器件的制造
    • JPS59127871A
    • 1984-07-23
    • JP380283
    • 1983-01-13
    • Nec Corp
    • BABA TOSHIO
    • H01L29/812H01L21/338H01L29/417H01L29/80
    • H01L29/80
    • PURPOSE:To form a gate and both a source and a drain through self-alignment, to lower gate-wiring resistance and to shorten gate length easily by making a forming process for one conductive type semiconductor layer, a coating proccess for an insulating film, a forming process for source and drain regions and a forming process for an operating layer contain. CONSTITUTION:The semiconductor layer 12 containing one conductive type impurity in high concentration is formed to the surface of a semi-insulating single crystal substrate 11, and the first insulating film 13 is applied on the layer 12. The first insulating film 13 and the semiconductor layer 12 in a region forming a gate are removed selectively to isolate the semiconductor layer 12, and the source and drain regions 12 are formed. One conductive type semiconductor layer 14 as the operating layer is grown in an isotropic manner, and a metallic layer 15 being in Schottky-contact with the semiconductor layer 14 is formed. The operating layer 14 and the gate electrode 15 are formed through selective removal. The second insulating film 16 is applied, and openings for a connection with the source and drain regions 12 are formed. A metallic layer 17 being in ohmic-contact is applied. The metallic layer 17 is removed selectively, and source and drain electrodes 17 are formed.
    • 目的:为了通过自对准形成栅极和源极和漏极,通过对一个导电型半导体层进行成形处理,可以容易地降低栅极布线电阻并缩短栅极长度,用于绝缘膜的涂层处理, 源区和漏区的形成过程和操作层的形成过程包含。 构成:在半绝缘性单晶基板11的表面形成含有高浓度导电型杂质的半导体层12,第一绝缘膜13被施加在层12上。第一绝缘膜13和半导体 选择性地去除形成栅极的区域中的层12以隔离半导体层12,并且形成源极和漏极区域12。 作为工作层的一个导电型半导体层14以各向同性的方式生长,形成与半导体层14肖特基接触的金属层15。 通过选择性去除形成工作层14和栅电极15。 施加第二绝缘膜16,形成用于与源区和漏区12连接的开口。 施加欧姆接触的金属层17。 选择性地去除金属层17,形成源极和漏极17。