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    • 2. 发明专利
    • SEMICONDUCTOR DEVICE
    • JP2001326336A
    • 2001-11-22
    • JP2001062178
    • 2001-03-06
    • TOSHIBA CORP
    • KOGA JUNJIUCHIDA KENOBA RYUJICHOKAI AKIRA
    • H01L27/10G11C11/38
    • PROBLEM TO BE SOLVED: To provide an element structure suitable for a high integration by realizing compatibility of a high speed operation and a low power consumption difficult in a conventional memory cell using a negative differentiating resistor and a load. SOLUTION: In a gate oxide film formed on a surface of a silicon substrate, a film on a source region is thinned. A first p type polycrystal silicon film, a tunnel oxide film and a second p type polycrystalline silicon film are sequentially laminated on a gate region. A source and the first silicon film constitute a high concentration impurity pn junction via a thin silicon oxide film to become an Esaki diode exhibiting the negative differentiating resistor. Meanwhile, a part between the first silicon film and the second silicon film becomes a nonlinear tunnel resistor to perform a role of load. The negative differentiating resistor and the load are connected in series between a low-voltage power source (ground) and a high-voltage power source Vdd to constitute a transistor containing a bistable circuit. Since potential information of the first silicon film of a memory node is read by a transistor amplification, it is rapid. Meanwhile, a current flowing between the power sources is suppressed to a low value, and a low power consumption at a waiting time is performed. An SRAM cell can be constituted of two elements with an excellent integration.
    • 4. 发明专利
    • PHASE SYNCHRONIZATION STORAGE DEVICE AND COMPUTING APPARATUS
    • JPH117760A
    • 1999-01-12
    • JP15709397
    • 1997-06-13
    • FUJITSU LTD
    • OSHIMA TOSHIO
    • G11C11/38H01L27/10H01L29/06H01L29/66H01L29/88H01L49/00
    • PROBLEM TO BE SOLVED: To guarantee that a specific phase state is maintained for a sufficiently long time and to make the error rate of information sufficiently small in a phase synchronization-type storage device and a computing apparatus in which a DC bias is applied to a very small tunnel junction single-electron-effect element, in which an AC pumping signal is applied so as to be phase-synchronized and in which information is stored and computed. SOLUTION: An auxiliary circuit 3, for error correction, which contains a device having the low error rate of information is installed. The refresh operation of information is performed from the auxiliary circuit 3 for error correction at a time interval which is shorter than the time in which a specific phase state is maintained stably. Alternatively, in order to store information which is contained in the time which is equal to, or more than, the time of the reciprocal number of the error rate of information, a plurality of phase synchronization-type storage circuits 1-1, 1-2 or computing circuits which are more than the number of stored bits of information are installed so as to be redundant. In addition, pieces of information which are outputted from the storage circuits or the computing circuits are decided by a majority vote. As a result, the error rate of information is made a sufficiently small value.