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51. 发明专利

JP2009009633A Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：JP2009009633A
公开(公告)日：2009-01-15
申请号：JP2007168947
申请日：2007-06-27
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： TOHO YOSHIROU , OISHI HAYATO , HARAGUCHI YOSHINORI , MATSUI YOSHINORI
IPC分类号： G11C11/401 , H01L21/8242 , H01L27/108
CPC分类号： G11C5/025 , G11C29/1201 , G11C29/26 , G11C29/48
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device which increases access speed and reduces a wiring area for an IO bus in the center of the chip by equalizing a distance between each memory cell and DQ pads to reduce variation in access time. SOLUTION: The semiconductor storage device has a memory cell array composed of blocks divided into a plurality of data IO pads, and the memory cell array is divided into a plurality of banks. The bank has a plurality of divided memory cell areas, the block formed by the memory cell area for each bank, and a preset number of data IO pads prepared correspondingly to the memory cell in the block. The IO pads are arranged in the vicinity of the corresponding block. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体存储装置，其通过均衡每个存储单元和DQ垫之间的距离来增加存取速度并减少用于芯片中心的IO总线的布线面积，以减少存取时间的变化。解决方案：半导体存储装置具有由划分成多个数据IO焊盘的块组成的存储单元阵列，并且存储单元阵列被分成多个存储体。存储体具有多个划分的存储单元区域，由每个存储体的存储单元区域形成的块以及对应于该块中的存储单元的预定数量的数据IO块。 IO垫布置在相应块的附近。版权所有（C）2009，JPO＆INPIT

52. 发明专利

JP2008192271A Semiconductor device and its test method 审中-公开
标题翻译：半导体器件及其测试方法
公开(公告)号：JP2008192271A
公开(公告)日：2008-08-21
申请号：JP2007028722
申请日：2007-02-08
申请人： Nec Electronics Corp , Necエレクトロニクス株式会社
发明人： HASHIMOTO KIYOKAZU , TSUNESADA NOBUTOSHI
IPC分类号： G11C29/34 , G01R31/28 , G11C16/02
CPC分类号： G11C29/52 , G11C16/04 , G11C16/3445 , G11C29/26 , G11C29/50004
摘要： PROBLEM TO BE SOLVED: To simultaneously test a first memory and a second memory of which data storage method is different from that of the first memory. SOLUTION: The semiconductor device (100) is equipped with the first memory (101) including a first memory cell array (10;10-1) divided into a plurality of sectors and an erase time setting register (14), and the second memory (102) including a second memory cell array (20;20-1) of which data storage method is different from that of the first memory cell array (10;10-1). First of all, a sector erase guarantee time to guarantee the erase time for erasing data stored in one sector is set to the erase time setting register (14). Next, a sector erase test is performed, by which the data stored in a selected sector among the plurality of sectors are erased within the sector erase guarantee time, and a data holding test is performed for the second memory cell array (20;20-1) in performing the sector erase test. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：同时测试与第一存储器不同的数据存储方法的第一存储器和第二存储器。解决方案：半导体器件（100）配备有包括划分成多个扇区的第一存储单元阵列（10; 10-1）和擦除时间设置寄存器（14）的第一存储器（101），以及所述第二存储器（102）包括数据存储方法与所述第一存储单元阵列（10; 10-1）不同的第二存储单元阵列（20; 20-1）。首先，擦除时间设定寄存器（14）设定扇区擦除保证时间，以保证将存储在一个扇区中的数据擦除的擦除时间。接下来，执行扇区擦除测试，通过该扇区擦除测试，在扇区擦除保证时间内擦除存储在多个扇区中的选定扇区中的数据，并且对第二存储单元阵列（20; 20- 1）执行扇区擦除测试。版权所有（C）2008，JPO＆INPIT

53. 发明专利

JP2007287305A Semiconductor memory element 审中-公开
标题翻译：半导体存储元件
公开(公告)号：JP2007287305A
公开(公告)日：2007-11-01
申请号：JP2007005108
申请日：2007-01-12
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクターHynix Semiconductor Inc.
发明人： DO CHANG-HO
IPC分类号： G11C29/12 , G01R31/28
CPC分类号： G11C29/48 , G11C29/1201 , G11C29/26 , G11C2029/1802
摘要： PROBLEM TO BE SOLVED: To provide semiconductor memory elements which can reduce the test time by making a DRAM core test by a parallel input/output interface method and support various input/output information transmission rates in the multi-port memory elements communicating information with external devices by a serial input/output interface method when operating normally. SOLUTION: The semiconductor memory element has multiple ports to support a serial input/output interface to communicate with outside devices through multiple first pads, multiple banks to transmit and receive information in parallel with those ports, multiple global data buses to support the information communication between those banks and ports, and a test mode controller to convert the serial input/output interface method into the parallel input/output interface method for the semiconductor memory elements and to make a core test in the test mode for the core areas of the banks. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供半导体存储器元件，其可以通过并行输入/输出接口方法进行DRAM内核测试来减少测试时间，并且支持多端口存储器元件通信中的各种输入/输出信息传输速率通过串行输入/输出接口方式的外部设备信息正常运行。解决方案：半导体存储器元件具有多个端口以支持串行输入/输出接口，以通过多个第一焊盘与多个第一焊盘通信，多个存储体与这些端口并行地发送和接收信息，多个全局数据总线以支持这些银行和端口之间的信息通信，以及将串行输入/输出接口方法转换为用于半导体存储器元件的并行输入/输出接口方法的测试模式控制器，并且在测试模式中进行核心测试银行。版权所有（C）2008，JPO＆INPIT

54. 发明专利

JP3970716B2 Semiconductor memory device and a method for testing 有权
公开(公告)号：JP3970716B2
公开(公告)日：2007-09-05
申请号：JP2002227058
申请日：2002-08-05
申请人：松下電器産業株式会社
发明人：博之貞方 , 直喜黒田
IPC分类号： G01R31/28 , G11C29/34 , G11C29/26
CPC分类号： G11C29/56004 , G11C29/26 , G11C2029/0401 , G11C2029/1806 , G11C2029/2602

55. 发明专利

JP2007514254A Integrated circuit, the test system, and a method for reading the error data from the integrated circuit 审中-公开
公开(公告)号：JP2007514254A
公开(公告)日：2007-05-31
申请号：JP2006536016
申请日：2004-10-16
申请人：インフィネオンテクノロジーズアクチエンゲゼルシャフト
发明人：フランコヴスキー，ゲルト
IPC分类号： G11C29/34 , G01R31/28 , G01R31/3193 , G11C29/00 , G11C29/26
CPC分类号： G11C29/26 , G11C2029/2602
摘要：【課題】各集積回路を試験する場合に試験機の各接続チャネル数を低減できて、エラーの発生や、コストを抑制できる集積回路、試験システムおよび試験方法を提供する。
【解決手段】エラーデータが試験モードに応じて読み出され、上記エラーデータを、第１および第２データ出力部を介してそれぞれ出力できる集積回路を設ける。集積回路に試験回路を、第１読み込み命令が印加されるとき、エラーデータを第１データ出力部に出力し、第２データ出力部を高インピーダンスに切り替え、第２読み込み命令が印加されるとき、エラーデータを第２データ出力部に出力し、第１データ出力部を高インピーダンスに切り替えるように設ける。

57. 发明专利

JP2005353060A Hub, memory module, memory system and reading method and writing method through memory system 有权
标题翻译： HUB，存储器模块，存储器系统和读取方法以及通过存储器系统的写入方法
公开(公告)号：JP2005353060A
公开(公告)日：2005-12-22
申请号：JP2005162842
申请日：2005-06-02
申请人： Samsung Electronics Co Ltd , 三星電子株式会社Samsung Electronics Co.,Ltd.
发明人： LEE KEE-HOON
IPC分类号： G06F12/16 , G11C5/00 , G11C29/26
CPC分类号： G06F13/1684 , G11C5/04 , G11C29/26 , G11C2029/2602 , G11C2029/4402
摘要： PROBLEM TO BE SOLVED: To provided a hub, memory module, memory system and reading method and writing method through the memory system. SOLUTION: In the hub, memory module, memory system and reading method and writing method, test writing and test reading can be carried out on all the memory modules, memory devices and memory units by bypassing identification information on the memory modules, memory devices and memory units in a test mode. Testing time can be reduced because simultaneous reading and writing on all the memory modules, memory devices and memory units can be carried out by bypassing the memory identification information. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过存储器系统提供集线器，存储器模块，存储器系统以及读取方法和写入方法。解决方案：在内存模块，存储器系统以及读取方式和写入方式中，可以通过绕过内存模块上的识别信息，对所有内存模块，内存设备和内存单元进行测试写入和测试读取，存储器件和存储器单元。可以通过绕过存储器识别信息来执行所有存储器模块，存储器件和存储器单元上的同时读取和写入，从而可以减少测试时间。版权所有（C）2006，JPO＆NCIPI

58. 发明专利

JP2005322375A Multiport memory element having serial input/output interface 有权
标题翻译：具有串行输入/输出接口的多个存储元件
公开(公告)号：JP2005322375A
公开(公告)日：2005-11-17
申请号：JP2004195067
申请日：2004-06-30
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクター
发明人： LEE IL-HO
IPC分类号： G01R31/28 , G11C5/02 , G11C7/10 , G11C8/16 , G11C11/401 , G11C11/4063 , G11C29/00 , G11C29/04 , G11C29/26
CPC分类号： G11C29/26 , G11C8/16
摘要： PROBLEM TO BE SOLVED: To provide a multiport memory element capable of testing operation without colliding with an internal command/address generation path through a restricted external pin.
SOLUTION: The multiport memory element, having a number of ports for supporting a serial input/output interface comprises a memory core; a control means for generating the internal command signal, an internal address signal, and a control signal by using commands inputted to the number of ports in a packet form and addresses; and a mode selection means for generating a test mode flag signal by combining signals applied to a number of mode selection pads. The input/output data assigned to transmission and reception pads by responding to the test mode flag signal are exchanged with a memory core via the ports, and the command assigned to the transmission and reception pads, the address, and the control signal are bypassed by the port and the control means and are provided to the memory core.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供能够测试操作的多端口存储器元件，而不会通过受限的外部引脚与内部命令/地址生成路径相冲突。解决方案：具有用于支持串行输入/输出接口的多个端口的多端口存储器元件包括存储器核心; 用于通过使用输入到分组形式的端口数量的命令和地址来产生内部命令信号，内部地址信号和控制信号的控制装置; 以及模式选择装置，用于通过组合施加到多个模式选择焊盘的信号来产生测试模式标志信号。通过响应于测试模式标志信号分配给发送和接收焊盘的输入/输出数据经由端口与存储器核心交换，分配给发送和接收焊盘，地址和控制信号的命令被旁路端口和控制装置，并被提供给存储器核心。版权所有（C）2006，JPO＆NCIPI

59. 发明专利

JP2005284700A Memory card 有权
标题翻译：存储卡
公开(公告)号：JP2005284700A
公开(公告)日：2005-10-13
申请号：JP2004097458
申请日：2004-03-30
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： ASARI SHINSUKE , SHINAGAWA CHIAKI , NAKAMURA YASUHIRO , KANAMORI SAKAKI , SHIRAISHI ATSUSHI
IPC分类号： G06F12/16 , G11C29/00 , G11C29/26
CPC分类号： G11C29/883 , G11C11/5635 , G11C16/04 , G11C29/26 , G11C29/76 , G11C29/88
摘要： PROBLEM TO BE SOLVED: To considerably lengthen the service life of a memory card following the occurrence of a defective block.
SOLUTION: A control logic searches the presence of an acquired defect in a block of a flash memory based on a defect factor code stored in a management information part of the flash memory, performs write/read comparison of data to the defective block in the case of detecting the defective block, and determines whether the block is normal. The block determined to be normal is registered as a normal block by rewriting a defect factor code of the corresponding block, and the registered block is stored as a writable block in a write management table of a management region. The originally normal block determined to be defective by an erratic error or the like can thereby be recovered.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：在发生故障块后，显着延长存储卡的使用寿命。解决方案：控制逻辑基于存储在闪速存储器的管理信息部分中的缺陷因子代码来检测闪速存储器块中获得的缺陷，执行数据到缺陷块的写/读比较在检测到故障块的情况下，判断块是否正常。被确定为正常的块通过重写相应块的缺陷因子代码而被注册为正常块，并且将注册块作为可写入块存储在管理区域的写入管理表中。因此可以恢复由误差等错误确定的原始正常块。版权所有（C）2006，JPO＆NCIPI

60. 发明专利

JP2004152299A Management for unworkable block in nonvolatile memory system 有权
标题翻译：非易失性存储系统中不可操作块的管理
公开(公告)号：JP2004152299A
公开(公告)日：2004-05-27
申请号：JP2003368138
申请日：2003-10-28
申请人： Sandisk Corp , サンディスクコーポレイションSanDisk Corporation
发明人： CHANG ROBERT C , QAWAMI BAHMAN , SABET-SHARGHI FARSHID
IPC分类号： G01R31/28 , G06F11/00 , G06F11/20 , G06F12/16 , G11C7/00 , G11C16/00 , G11C16/02 , G11C16/34 , G11C29/00 , G11C29/04 , G11C29/26 , G11C29/44 , G11C29/56
CPC分类号： G11C29/26 , G11C16/04 , G11C29/44
摘要： PROBLEM TO BE SOLVED: To use a block identified as a defective block but usable potentially as a spare block. SOLUTION: This invention includes a process for subjecting at least one physical block identified as a defective one inside a nonvolatile memory 124 to an inspection, in which it is determined whether the defective physical block can be used or not, a process for determining a case that the physical block identified as a defective one passes the inspection, a process for identifying the physical block, which is identified as a defective one, as a usable physical block when the physical block identified as a defective one passes the inspection. COPYRIGHT: (C)2004,JPO

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