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1. 发明专利

JP2009009665A Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：JP2009009665A
公开(公告)日：2009-01-15
申请号：JP2007171979
申请日：2007-06-29
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： TOHO YOSHIROU , OISHI HAYATO , HARAGUCHI YOSHINORI , MATSUI YOSHINORI
IPC分类号： G11C11/4096 , G11C11/4091 , G11C11/4093
CPC分类号： G11C7/1048 , G11C7/1051 , G11C7/1069
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device which improves precharge speed of data IO lines and data amplifiers without increasing current consumption to increase speed in reading and writing data from and into memory.
SOLUTION: The semiconductor storage device comprises a column decoder for generating a column selection signal to select any of a plurality of bit lines connected to the memory cells corresponding to inputted column address, a bit line selection switch for connecting any of a plurality of the bit line pairs with data IO line pairs to output the data read from the memory cell to the outside by the column selection signal, a data amplifier for amplifying a difference between the data IO line pairs to output the read data to an output buffer, a data IO switch provided for the data IO line, an IO precharge circuit for precharging the data IO line pair except for the data amplifier, and an amplifier precharge circuit for precharging the IO line pair of the data amp.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种提高数据IO线和数据放大器的预充电速度的半导体存储装置，而不增加电流消耗，从而提高从存储器读取数据的速度。解决方案：半导体存储装置包括列解码器，用于产生列选择信号，以选择与输入的列地址相对应的与存储单元连接的多个位线中的任何一个位线;位线选择开关，用于连接多个与数据IO线对的位线对，通过列选择信号将从存储器单元读取的数据输出到外部;数据放大器，用于放大数据IO线对之间的差异，以将读取的数据输出到输出缓冲器为数据IO线提供的数据IO开关，用于对数据放大器以外的数据IO线对进行预充电的IO预充电电路和用于对数据放大器的IO线对进行预充电的放大器预充电电路。版权所有（C）2009，JPO＆INPIT

2. 发明专利

JP2013037734A Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：JP2013037734A
公开(公告)日：2013-02-21
申请号：JP2011171652
申请日：2011-08-05
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： OISHI HAYATO , NAGAMINE HISASHI
IPC分类号： G11C11/401 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
CPC分类号： G11C8/12 , G11C5/063 , G11C11/4096 , G11C11/4097 , G11C2207/005
摘要： PROBLEM TO BE SOLVED: To simultaneously supply a timing signal from a control line extending in an X direction to two circuit blocks adjacent to each other in a Y direction.SOLUTION: A semiconductor device includes ports PT1 and PT2 arranged in a Y direction, circuits C1 and C2 respectively connected to the ports PT1 and PT2, and a control line CTL1 extending in an X direction to commonly control subcircuits SC1 and SC2 included in the circuits C1 and C2. A coordinate Y1 being an intermediate coordinate in the Y direction between the subcircuits SC1 and SC2 is different from an intermediate coordinate Y0 in the Y direction between the ports PT1 and PT2. Distances from the control line CTL1 to the subcircuits SC1 and SC2 in the Y direction are equal. Thus, operation timings of the circuits C1 and C2 are accurately matched with each other. Moreover, even when a plurality of control lines is necessary, distances to corresponding subcircuits are set constant for each control line.
摘要翻译：要解决的问题：同时从Y方向上延伸的控制线向Y方向相邻的两个电路块提供定时信号。解决方案：半导体器件包括沿Y方向布置的端口PT1和PT2，分别连接到端口PT1和PT2的电路C1和C2以及沿X方向延伸的控制线CTL1以共同控制包括的子电路SC1和SC2 在电路C1和C2中。在子电路SC1和SC2之间的Y方向上的中间坐标的坐标Y1与端口PT1和PT2之间的Y方向上的中间坐标Y0不同。在Y方向上从控制线CTL1到子电路SC1和SC2的距离相等。因此，电路C1和C2的操作定时彼此精确地匹配。此外，即使在需要多条控制线的情况下，对于各控制线，对于相应的子电路的距离设定为一定。版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2011109025A Method and apparatus for automatically disposing cells for semiconductor integrated circuit, and program therefor 审中-公开
标题翻译：用于半导体集成电路自动处理电池的方法和装置及其程序
公开(公告)号：JP2011109025A
公开(公告)日：2011-06-02
申请号：JP2009265355
申请日：2009-11-20
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： OISHI HAYATO
IPC分类号： H01L21/82 , G06F17/50
摘要： PROBLEM TO BE SOLVED: To provide a method and an apparatus for automatically disposing cells for a semiconductor integrated circuit in which, when disposing cells of different manufacturing steps while mixing them, the cells are disposed without expanding the area, and a program therefor.
SOLUTION: The method includes a cell appearance setting step and an automatic cell disposing step. In the cell appearance setting step, first appearance is set in such a size that a kind of cell can be disposed adjacently to the same kind of cell, among various cells, and a different kind of cell can not be disposed adjacently thereto and for the other kind of cell, such larger appearance is set that cells can be disposed adjacently regardless of kinds of cells including the cells to which the first appearance is set. In the automatic cell disposing step, various cells are automatically disposed while using cells having the appearance set in the cell appearance setting step.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：提供一种用于半导体集成电路的自动配置单元的方法和装置，其中，当在混合不同的制造步骤的单元的同时设置单元，而不扩大该区域，并且程序为此。解决方案：该方法包括单元格外观设置步骤和自动单元布置步骤。在单元格外观设定步骤中，首先将外观设定为可以在各种单元格中，将单元的种类与相同种类的单元相邻配置，并且不能将其与不同种类的单元相邻配置，设置其他种类的细胞，无论细胞的种类如何，都可以相邻地配置细胞，这些细胞包括设置有第一外观的细胞。在自动细胞处理步骤中，在使用在细胞外观设定步骤中设定的外观的细胞的情况下，自动配置各种细胞。版权所有（C）2011，JPO＆INPIT

4. 发明专利

JP2009295854A Through-hole layout apparatus, and through-hole layout method 有权
标题翻译：通孔式布局设备，以及通孔式布局方法
公开(公告)号：JP2009295854A
公开(公告)日：2009-12-17
申请号：JP2008149172
申请日：2008-06-06
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： OISHI HAYATO , MATSUKI KAZUHIKO
IPC分类号： H01L21/82 , G06F17/50
CPC分类号： G06F17/5068 , G06F17/5077
摘要： PROBLEM TO BE SOLVED: To reduce the difference among values of layout density of through-holes on a semiconductor integrated circuit. SOLUTION: This through-hole layout apparatus includes: an extraction part extracting existing through-holes connecting upper-layer wiring to lower-layer wiring from design data of the semiconductor integrated circuit; a calculation part calculating a layout density in a predetermined range around each of through-holes extracted by the extraction part, for the each through-holes; a selection part selecting, as target through-holes, the through-holes each having the layout density calculated by the calculation part smaller than a predetermined value, from among the through-holes extracted by the extraction part; and an additional layout part determining predetermined positions in the predetermined range centering the target through-holes as additional layout positions of through-holes, and additionally arranging the through-holes at additional layout positions on design data. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：减少半导体集成电路上的通孔布局密度值之间的差异。解决方案：该通孔布局装置包括：提取部，从半导体集成电路的设计数据提取连接上层布线到下层布线的现有通孔; 对于每个通孔，计算由提取部提取的每个通孔周围的预定范围内的布局密度的计算部分; 选择部，从由所述提取部提取的所述通孔中选择各自具有由所述计算部算出的布局密度小于预定值的通孔作为目标通孔; 以及附加布局部分，其以预定的范围确定作为目标通孔的预定范围，作为通孔的附加布局位置，并且在设计数据的附加布局位置附加布置通孔。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2009009633A Semiconductor storage device 审中-公开
标题翻译：半导体存储设备
公开(公告)号：JP2009009633A
公开(公告)日：2009-01-15
申请号：JP2007168947
申请日：2007-06-27
申请人： Elpida Memory Inc , エルピーダメモリ株式会社
发明人： TOHO YOSHIROU , OISHI HAYATO , HARAGUCHI YOSHINORI , MATSUI YOSHINORI
IPC分类号： G11C11/401 , H01L21/8242 , H01L27/108
CPC分类号： G11C5/025 , G11C29/1201 , G11C29/26 , G11C29/48
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device which increases access speed and reduces a wiring area for an IO bus in the center of the chip by equalizing a distance between each memory cell and DQ pads to reduce variation in access time. SOLUTION: The semiconductor storage device has a memory cell array composed of blocks divided into a plurality of data IO pads, and the memory cell array is divided into a plurality of banks. The bank has a plurality of divided memory cell areas, the block formed by the memory cell area for each bank, and a preset number of data IO pads prepared correspondingly to the memory cell in the block. The IO pads are arranged in the vicinity of the corresponding block. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体存储装置，其通过均衡每个存储单元和DQ垫之间的距离来增加存取速度并减少用于芯片中心的IO总线的布线面积，以减少存取时间的变化。解决方案：半导体存储装置具有由划分成多个数据IO焊盘的块组成的存储单元阵列，并且存储单元阵列被分成多个存储体。存储体具有多个划分的存储单元区域，由每个存储体的存储单元区域形成的块以及对应于该块中的存储单元的预定数量的数据IO块。 IO垫布置在相应块的附近。版权所有（C）2009，JPO＆INPIT

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