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51. 发明专利

JPS56149660A COMPOSITE COMPUTER SYSTEM 失效
公开(公告)号：JPS56149660A
公开(公告)日：1981-11-19
申请号：JP5288580
申请日：1980-04-23
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： URUGA HIDEO , TAKENOUCHI HIROO , HATADA MINORU , HIYAMA KUNIO , SHIMIZU ISAO , TODA AKIRA , IMAI MITSURU , INAMORI HISAYOSHI
IPC分类号： G06F15/16 , G06F13/36 , G06F15/177
摘要： PURPOSE:To shorten the queuing time for use of data bus, by detecting at a high- speed the fact that all processors are idle through a simple constitution. CONSTITUTION:Plural processors P0-Pn are connected to the common data bus D via the communication devices C0-Cn, and a communication of data a given among the processors. The processor P consists of the communication device C, idle control flip-flop FF, OR circuit and open collector gate G. The device C corresponding to the receiving processor P sets the idle control FF when the reception of data starts to cancel an idle state, and the receiver side is set under the idle state when the transmission of data is over. Thus an idle control is possible for the system as a whole. In such way, the idle state is detected with a simple constitution of the circuit.

52. 发明专利

JPS5563458A PROCESSOR SELECTION SYSTEM IN MULTIIPROCESSOR SYSTEM 失效
公开(公告)号：JPS5563458A
公开(公告)日：1980-05-13
申请号：JP13583378
申请日：1978-11-06
申请人： HITACHI LTD
发明人： HIYAMA KUNIO , KOUNO SHIYUNEI , SHIYOUDA AKIO , TOKITA YOSHIAKI
IPC分类号： H04Q3/545 , G06F9/52 , G06F13/00 , G06F15/16 , G06F15/177
摘要： PURPOSE:To increase the extensibility of system, by equally operating a plurality of processors and performing equal processing, when the interruption request is caused from a plurality of processors, in the multi-processor system. CONSTITUTION:The system time counter 6 counts the number of times of interruption caused at the entire system and controls the interval of execution for the processing. When the processor 1 causes interruption for the content of the counter 6 every interruption, the exclusive control means 5 selects the sole processor 1. When the content of the counters 3 and 6 is in agreement with each other, the comparison means 2 equally advances the counters 3 and 6 via the step means 4. Where the processor 1 receives the said coincidence signal, it performs the operation as the master processor. Since the control system for each processor is unified, the extensibility of system can be increased.

53. 发明专利

JPS5559537A NETWORK CONTROL SYSTEM 失效
公开(公告)号：JPS5559537A
公开(公告)日：1980-05-06
申请号：JP13265778
申请日：1978-10-30
申请人： HITACHI LTD
发明人： HATADA MINORU , HIYAMA KUNIO , IHARA KOUICHI
IPC分类号： G06F13/00
摘要： PURPOSE:To simplify the communication control by forming the network system with plural number of the single-way loop-type transmission line and then providing communication control exclusive processor NCP at each node and in correspondence to the loop. CONSTITUTION:The network constitution is limited to the form which is formed by combining plural number of the single-way loop-type transmission line as shown in Fig. (a), and NCP is provided at each node in correspondence to the loop. At NCP1 the data given from the loop is stored in data memory R32 through reception circuit 31. The data is decided at distributor circuit 33 according to the destination address. And in the case of host computer HST, for example, the data is transferred to HST42 via compound circuit 38 and data exchange unit 40. In case the address is the adjacent loop, the data is transferred to NCP243 via compound circuit 39 and data exchange unit 41. On the other hand, the data from HST42 is stored in data memory S35 and then transmitted to loop bus bis transmission circuit 37 or transferred to NCP243 through transmission circuit 37 according to the destination address.

54. 发明专利

JPS5447546A PROGRAM LOADING METHOD FOR MULTIPLE PROCESS SYSTEM 失效
公开(公告)号：JPS5447546A
公开(公告)日：1979-04-14
申请号：JP11334177
申请日：1977-09-22
申请人： HITACHI LTD
发明人： NAITOU ICHIROU , WATANABE MICHIO , HIYAMA KUNIO
IPC分类号： G06F15/177 , G06F9/445 , G06F12/00 , G06F12/06 , G06F15/16
摘要： PURPOSE:To realize the cost reduction by providing the means which stores the information to be loaded into the common memory from the processor containing the program input device and then transfers the information to the local memory of other processor. CONSTITUTION:The program data given from input device 5 is stored in data buffer region 3a of common memory 3 via processor 1a. While processor 1b reads out the transfer program stored in ROM2b1 which is part of local memory 2b and carries out this program to tranfer the program data which is stored in data buffer region 3a to be loaded to local memory 2b. As a result, the program data can be loaded to the local memories of multiple processors via only one unit of the input device, thus lowering the cost with the facilitated operation.

55. 发明专利

JPS5439503A PRIORITY SELECTION SYSTEM IN RING TRANSMISSION LINE 失效
公开(公告)号：JPS5439503A
公开(公告)日：1979-03-27
申请号：JP10584277
申请日：1977-09-05
申请人： HITACHI LTD
发明人： HIYAMA KUNIO
IPC分类号： G06F13/00 , G06F15/16 , G06F15/173 , H04L12/42
摘要： PURPOSE:To enable to use the transmission line efficiently, by giving priority to the transmission request and the delivery request in each delivery line control circuit.

56. 发明专利

JPS52133737A DIGIT DESIGN ATION SYSTEM 失效
公开(公告)号：JPS52133737A
公开(公告)日：1977-11-09
申请号：JP4993576
申请日：1976-05-04
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： YASUI ISAMU , HIYAMA KUNIO , NIWA AKIO , MORI MASAHARU
IPC分类号： G06F7/00 , G06F7/76
摘要： PURPOSE:To perform calculation with the shift circuit comprising the basic data bus and the arithmetic circuit along with the mask pattern generation circuit and the work register for temporary storage of the calculation result, and thus to perform the digit designation, decreasing the hardware quantity.

57. 发明专利

JPS52101937A INDEX ADDING METHOD 失效
公开(公告)号：JPS52101937A
公开(公告)日：1977-08-26
申请号：JP1929576
申请日：1976-02-23
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , HITACHI LTD , FUJITSU LTD
发明人： OOKAWA KAZUMASA , HONMA KATSUTOSHI , NAITOU ISAO , HIYAMA KUNIO , FUJIMATSU TOSHIHIKO
IPC分类号： G06F9/355
摘要： PURPOSE:To reduce the calculation cycle, minimize the hardware and simplify the control method and to realize the economical command processing by using a two-input adder to execute the index calculation processing.

58. 发明专利

JPH03272232A INDEPENDENT SYNCHRONIZING TYPE LOCAL AREA NETWORK 失效
公开(公告)号：JPH03272232A
公开(公告)日：1991-12-03
申请号：JP6977990
申请日：1990-03-22
申请人： HITACHI LTD
发明人： AMADA EIICHI , HIYAMA KUNIO , KOBAYASHI NAOYA , TAKIYASU YOSHIHIRO , HATAKEYAMA YASUHIKO , NAKAYAMA HARUYUKI
IPC分类号： H04L7/00 , H04J3/06 , H04L12/42 , H04Q11/04
摘要： PURPOSE:To make a physical transmission speed nearly equal to an information transmission speed by detecting the periodicity of a frame synchronization pattern so as to recognize a frame starting position. CONSTITUTION:A multi-medium LAN uses an external clock 9 supplied externally as a common synchronous clock to distribute it to all nodes, and each node supplies the clock to a synchronization system terminal equipment connectd to the node. Moreover, the information transfer speed is decided by outputting a VC-4 synchronously with the external clock 9. Each node relays the synchronous clock information in common from a master node 2-8 to a succeeding node by using a repeater. Each node reduces a clock jitter generated at the relay of the clock through a phase synchronizing loop 13-9 and applies a synchronous clock to a synchronous system device 7-2. Moreover, a each node has an oscillator for its own station to decide a frame period and to send it to a succeeding node.

59. 发明专利

JPH02276339A HIGH-SPEED RING LAN SYSTEM AND LAN NODE 失效
公开(公告)号：JPH02276339A
公开(公告)日：1990-11-13
申请号：JP32845789
申请日：1989-12-20
申请人： HITACHI LTD
发明人： TAKIYASU YOSHIHIRO , TANAKA KATSUKI , AMADA EIICHI , SUZUKI TAHEI , YAMAUCHI YUKIJI , YAMAGA MITSUHIRO , TERADA MATSUAKI , HIYAMA KUNIO
IPC分类号： H04L12/42
摘要： PURPOSE:To store two or more low-order networks, especially, public networks and LANs different in signal transmission speed by providing each of plural node devices, which are connected to one another by a ring transmission line, with interface means for the storage of low-order networks and switching fixed length packets between interface means and communication frames. CONSTITUTION:A high-order LAN 200 is constituted of nodes 1A to 1D and a transmission line 2, and a low-order network 201 constituted of nodes 3A and 3B and an optical fiber transmission line 4 is connected to the node 1A, and a low-order network 202 constituted of nodes 5A and 5B and a transmission line 6 is connected to the node 2A. Each of nodes 1A to 1D of the high-order LAN is provided with plural low-order network interfaces (user device interfaces), and one node can store plural input/output devices or low-order networks. At the time of constituting a network system, a 9-bit output terminal address unique in the system is given to the output terminal of each node which is connected to a low-order network interface.

60. 发明专利

JPS63175596A REMOTE POWER FEEDING METHOD FOR COMMUNICATION NETWORK SYSTEM 失效
公开(公告)号：JPS63175596A
公开(公告)日：1988-07-19
申请号：JP598687
申请日：1987-01-16
申请人： HITACHI LTD , NIPPON STEEL CORP
发明人： YONEMOTO MASATOSHI , TAKAGISHI YASUYUKI , HASHIMOTO TOYOKAZU , MATSUYAMA FUMIO , HIYAMA KUNIO , YAMAMOTO OSAMU
IPC分类号： H04Q9/00
摘要： PURPOSE:To realize power feeding to an optional device without increasing the power supply capability of a sender by allowing all stations to be capable of sending/receiving power and releasing the limit of distance at each installation of the station. CONSTITUTION:Communication controllers 1-6 are provided and communication is attained through an optical fiber cable 7. The optical signal is sent/received in the order of communication controller 1 communication controller 2 ... communication controller 6. Each station is provided with a means for supplying power to its own repeater, a means for feeding power to its own repeater by the power supply from other station and a means for feeding power to repeaters of other stations, all the stations are formed to be capable of receiving/sending power and other station within a distance limit is selected as a sender station. For example, the communication controller 4 sends power to the communication controllers 2, 3 and the communication controllers 2, 3 receive power from the communication controller 4. Thus, the relation of the transmission/reception is selected freely within the distance limit and power is supplied to an optional communication controller within the range.

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