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1. 发明专利

JPS56149660A COMPOSITE COMPUTER SYSTEM 失效
公开(公告)号：JPS56149660A
公开(公告)日：1981-11-19
申请号：JP5288580
申请日：1980-04-23
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： URUGA HIDEO , TAKENOUCHI HIROO , HATADA MINORU , HIYAMA KUNIO , SHIMIZU ISAO , TODA AKIRA , IMAI MITSURU , INAMORI HISAYOSHI
IPC分类号： G06F15/16 , G06F13/36 , G06F15/177
摘要： PURPOSE:To shorten the queuing time for use of data bus, by detecting at a high- speed the fact that all processors are idle through a simple constitution. CONSTITUTION:Plural processors P0-Pn are connected to the common data bus D via the communication devices C0-Cn, and a communication of data a given among the processors. The processor P consists of the communication device C, idle control flip-flop FF, OR circuit and open collector gate G. The device C corresponding to the receiving processor P sets the idle control FF when the reception of data starts to cancel an idle state, and the receiver side is set under the idle state when the transmission of data is over. Thus an idle control is possible for the system as a whole. In such way, the idle state is detected with a simple constitution of the circuit.

2. 发明专利

JPS635788B2 失效
公开(公告)号：JPS635788B2
公开(公告)日：1988-02-05
申请号：JP2950583
申请日：1983-02-25
申请人： HITACHI LTD
发明人： HATADA MINORU
IPC分类号： G06F15/16 , G06F13/374 , G06F15/177

3. 发明专利

JPS6033656A PROCESSOR RECOGNIZING SYSTEM OF MULTI-PROCESSOR SYSTEM 失效
公开(公告)号：JPS6033656A
公开(公告)日：1985-02-21
申请号：JP14254983
申请日：1983-08-05
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： ISHIDA HIDEAKI , MATSUSHITA MASATOSHI , HATADA MINORU
IPC分类号： G06F15/16 , G06F13/14 , G06F13/364 , G06F15/177
摘要： PURPOSE:To execute easily the recognition of a processor by providing a different value to each processor even if plural processors are started from the same address, by providing an encoder in a bus arbiter, and latching the output of the encoder. CONSTITUTION:In a bus srbiter and a processor recognizing circuit, an encoder is used in the bus arbiter. The output of this encoder EC is latched by an F/F 2 by a timing by which an F/F1 for outputting a bus use permitting signal BG is latched. Outputs (A0-A2) of the encoder EC in case when the F/F1 and the F/F2 are latched are the same as a vlue which has encoded a signal BGi (i=0, 1, 3 and 4). An output enable OE of the F/F2 uses a chip select inversion CS signal from an address decoder AD. Also, the output of the F/F2 is connected to a data bus. In such a way, in case of each processor executes a read access to the same address, the processor can be recognized easily by providing a different value to each processor.

4. 发明专利

JPS59226542A PROCESSING LINE SETTING SYSTEM OF COMMUNICATION PROCESSOR 失效
公开(公告)号：JPS59226542A
公开(公告)日：1984-12-19
申请号：JP10078583
申请日：1983-06-08
申请人： HITACHI LTD
发明人： IWAI TOKUYUKI , HATADA MINORU
IPC分类号： H04L29/14 , G06F13/40 , H04L13/00
摘要： PURPOSE:To set dynamically the correspondence between processors and processing communication lines by using a switching circuit, which can be set with software, as the switch for this correspondence. CONSTITUTION:Lines 0-5 are connected to switching circuits SW through communication interface circuits C.I/F. The other ends of individual switching SW are connected to processors P0-P2, and the correspondence between communication interface circuits C.I/F and processors P0-P2 is set by two-bit control terminals. A signal for the correspondence is generated by an ad dress decoder AD and is latched in a latch circuit L and is supplied to individual switching circuits SW.

5. 发明专利

JPS58176782A FINGERPRINT COLLATING PROCESSOR SYSTEM 失效
公开(公告)号：JPS58176782A
公开(公告)日：1983-10-17
申请号：JP5905582
申请日：1982-04-09
申请人： HITACHI LTD
发明人： TSUBOI AKIRA , HAYASHI TAKANARI , HONMA KOUICHI , YAMAGATA NOBUTAKE , HATADA MINORU , KONDOU AKIHIRO
IPC分类号： G06T7/00 , G06K9/00
摘要： PURPOSE:To shorten the processing time for collation of fingerprint and to improve the reliability of collation, by using plural collating processors to collate each feature point of a fingerprint and controlling these collations by a control processor. CONSTITUTION:A control processor 1O stores the chip pictures and the segment pictures of all registered feature points of a person who is receiving a check of fingerprint into a receiving memory 3O and then delivers a collation start command after transmitting the data on the chip and seqment pictures, etc. concerning the feature point alpha (alpha=0, 1...n) to a collating processor 1. While the processor 1 receives these data the store them into a memory 3alpha to start collations in response to a collation start command. Then the chip picture is superposed on the segment picture to evaluate the resembrance between both pictures. Thus the way of superposition that has the highest resembrance is search?ed, and then the propriety of collation is decided.

6. 发明专利

JPS56118127A DATA TRANSMISSION SYSTEM AND BUS COUPLER 失效
公开(公告)号：JPS56118127A
公开(公告)日：1981-09-17
申请号：JP2050280
申请日：1980-02-22
申请人： HITACHI LTD
发明人： URUGA HIDEO , TAKENOUCHI HIROO , HATADA MINORU , HIYAMA KUNIO
IPC分类号： G06F13/36 , G06F9/52 , G06F13/40 , G06F15/16 , G06F15/173 , G06F15/177
摘要： PURPOSE:To simplify the constitution of the entire system, by making the upper- rank and lower-rank bus couplers with the same circuit constitution. CONSTITUTION:Gates G1, G2, G4 control the transmission signal input to terminals S1, A1, D1 to be output at terminals S2, A2, D2, and the switching of the gates is controlled with the output of a competition control circuit ARB. Gates G3, G5 control the signal for reception inputted to the terminals A2, D2 to be output at the terminals A1, D1, and the on/off of the gates is controlled with the output of comparators CMPL, CMPH. CMPL compares the content of an address setter ASETL with the signal at the terminal A2, and CMPH compares the content of the address setter ASETH with the signal at the terminal A2.

7. 发明专利

JPS55147850A LOOP SYSTEM CONTROLLING SYSTEM 失效
公开(公告)号：JPS55147850A
公开(公告)日：1980-11-18
申请号：JP5573079
申请日：1979-05-09
申请人： HITACHI LTD
发明人： HATADA MINORU , HIYAMA KUNIO , IHARA KOUICHI , IWAI TOKUYUKI
IPC分类号： G06F13/00 , H04L12/437
摘要： PURPOSE:To make it possible to transmit a command signal to all nodes simultaneously, by providing a signal generating circuit, which generates the command signal of a prescribed time width, in each node, in the network system coupled by one-direction loop buses. CONSTITUTION:When command signal (fault signal and so on) V0 of a prescribed time width is generated in node Ni, signal V0 is transmitted to succeeding-stage node Ni+1 and node Ni itself through pulse width shortening circuit 35 and OR gate 34. In case that signal V0 is not generated, the signal from preceding-stage node Ni-1 is transmitted to node Ni itself and succeeding-stage node Ni+1 through AND gate 32 and OR gate 34. Here, if the time width of signal V0 is set to a value larger than the loop one-circulation time, the signal circulated once cannot be taken into node Ni due to the AND gate.

8. 发明专利

JPS55105728A COMPOSITE COMPUTER SYSTEM 失效
公开(公告)号：JPS55105728A
公开(公告)日：1980-08-13
申请号：JP1334579
申请日：1979-02-09
申请人： HITACHI LTD
发明人： URUGA HIDEO , HATADA MINORU , HIYAMA KUNIO , IHARA KOUICHI
IPC分类号： G06F13/36 , G06F3/00 , G06F13/38 , G06F15/16
摘要： PURPOSE:To enable to change the scale and constitution in response to the system requirement flexibly, by providing the common memory, common bus, a plurality of processors, a plurality of memory request circuits corresponding to each processor, and competition prevention unit for the common bus, for each cluster. CONSTITUTION:At least one of a plurality of processors 11a-11n is provided with at least two memory request circuits 12n1, 12n2. The one unit of this fundamental constitution is referred to as cluster. At least one of the two memory request circuits connects the corresponding processor 11n to the bus 13 of the cluster 10 to which the processor 11n belongs, so that the processor 11n can access to the common memory 14 of the cluster 10 to which the processor 11n belongs. The cluster 10 is provided with the memory switch 15 controlling the competition of the bus 13. The constitution in the cluster 20 is entirely the same as that of the cluster 10. As a result, the processor 11n in the cluster 20 can access to the common memory 24 in the cluster 20 as well as the common memory 14.

9. 发明专利

JPS53132227A OUTPUT UNIT FOR VIDEO DATA 失效
公开(公告)号：JPS53132227A
公开(公告)日：1978-11-17
申请号：JP4681377
申请日：1977-04-25
申请人： HITACHI LTD
发明人： HATADA MINORU
IPC分类号： G09G5/00 , G06F3/14 , G09G5/36 , G09G5/393 , G09G5/395
摘要： PURPOSE:To remarkably simplify the circuit, by executing the renewal of the address data of memory units and the generation of synchronizing signals with a microprocessor, in an output unit of video data.

10. 发明专利

JPS6225072A DOCUMENT FORMING APPARATUS 失效
公开(公告)号：JPS6225072A
公开(公告)日：1987-02-03
申请号：JP16409585
申请日：1985-07-26
申请人： HITACHI LTD
发明人： OKADA KUNIHIRO , ARAKAKI MASAKAZU , HATADA MINORU , MESE MICHIHIRO
IPC分类号： G06F3/12 , B41J3/46 , B41J5/30 , B41J29/42 , B41J29/52
摘要： PURPOSE:To enable to print a beautiful character at a target position without failure by superposing a character size to be printed and a printing range on a form before printing to indicate them, thereby printing a document at the prescribed position on the form. CONSTITUTION:A transmission type display 203 of a plane display unit 10 has a printing position indicator 213 for indicating the size, position and length of a character to be printed on a form 12 in a simulating manner and a reference line indicator 214 for indicating a reference line. The form 12 is conveyed to the back side of the display unit 10, and the lower end of a line desired to be initially printed is matched to the reference line. A printing head is moved to a print starting position to confirm the content of a character row indicated on a reflecting type display 201. Then, the positional relationship of the character indicated on the display 213 and the form 12 is confirmed, and the form 12 is printed. When the printing is finished, the form 12 is fed at the prescribed distance to confirm the printing result through a transparent unit 202 or a transparent unit 204. This operation is repeated to form an accurately positioned formed document.

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