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41. 发明专利

JP4936344B1 Metal film forming method, and products with a metal film 有权
标题翻译：空值
公开(公告)号：JP4936344B1
公开(公告)日：2012-05-23
申请号：JP2011553643
申请日：2011-09-30
申请人：株式会社いおう化学研究所 , 株式会社メイコー , 邦夫森
发明人：学宮脇 , 孝廣工藤 , 祐亮松野 , 克仁森 , 邦夫森 , 茂道脇
IPC分类号： C23C18/20 , C25D5/56 , H05K3/18
CPC分类号： C23C18/1608 , C23C18/1612 , C23C18/1653 , C23C18/20 , C23C18/204 , C23C18/2086 , C23C18/285 , C23C18/30 , C25D5/56 , C25D11/00 , H05K3/389 , H05K2203/072 , H05K2203/122 , H05K2203/124 , Y10T428/31663 , Y10T428/31678
摘要：金属膜が剥離し難い配線基板を提供することである。
基体表面に下記化合物（α）を含む剤が設けられる工程（Ｘ）と、前記化合物（α）の表面に、湿式メッキの手法により、金属膜が設けられる工程（Ｙ）とを具備してなり、前記化合物（α）は、一分子内に、ＯＨ基またはＯＨ生成基と、アジド基と、トリアジン環とを有する化合物であり、前記基体はポリマーが用いられて構成されてなる。
【選択図】なし
摘要翻译：本发明的目的在于提供一种金属膜不容易脱离的布线基板。一种形成金属膜的方法包括在化合物（a）的表面上将含有化合物（a）的试剂施加到基材表面上的步骤（X）和在化合物（a）的表面上形成金属膜的步骤（Y）湿式电镀技术，其中化合物（a）是每分子具有OH基或OH生成基团，叠氮基和三嗪环的化合物，并且所述碱包含聚合物。

42. 发明专利

JP2010239133A Metal-clad laminate 有权
标题翻译：金属层压板
公开(公告)号：JP2010239133A
公开(公告)日：2010-10-21
申请号：JP2010055956
申请日：2010-03-12
申请人： Ajinomoto Co Inc , 味の素株式会社
发明人： NARABASHI HIROHISA , NAKAMURA SHIGEO , YOKOTA TADAHIKO
IPC分类号： H05K3/18 , B32B15/08 , H05K3/00
CPC分类号： H05K3/381 , H05K3/025 , H05K2203/072 , H05K2203/0786 , H05K2203/1152 , Y10T29/49155
摘要： PROBLEM TO BE SOLVED: To obtain a metal-clad laminate in which a conductor layer having superior peel strength is formed on a smooth surface of an insulating layer. SOLUTION: A method of manufacturing the metal-clad laminate includes (A) a step of preparing a metal-clad laminate precursor by providing one or more sheets of prepreg between two sheets of film having a metal film layer on a support layer, and heating and pressing them under reduced pressure, (B) a step of removing the support layer, (C) a step of removing the metal film layer, and (D) a step of forming a metal film layer on the surface of an insulating layer by electroless plating. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了获得在绝缘层的光滑表面上形成具有优良剥离强度的导体层的覆金属层压板。解决方案：一种制造覆金属层压板的方法包括（A）通过在支撑层上具有金属膜层的两片膜之间设置一层或多片预浸料来制备覆金属层压板前体的步骤（B）除去支撑层的步骤，（C）除去金属膜层的工序，（D）在金属膜层的表面形成金属膜层的工序，绝缘层通过无电镀。版权所有（C）2011，JPO＆INPIT

43. 发明专利

JP2009239278A Substrate for mounting electronic component, and method of manufacturing the same 审中-公开
标题翻译：用于安装电子部件的基板及其制造方法
公开(公告)号：JP2009239278A
公开(公告)日：2009-10-15
申请号：JP2009052876
申请日：2009-03-06
申请人： Ibiden Co Ltd , イビデン株式会社
发明人： WATANABE HIROYUKI
IPC分类号： H01L21/60 , H01L23/12
CPC分类号： H05K3/3457 , H01L23/49816 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/05568 , H01L2224/05573 , H01L2224/05624 , H01L2224/1134 , H01L2224/11822 , H01L2224/13019 , H01L2224/13144 , H01L2224/81193 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H05K2203/0435 , H05K2203/072 , H05K2203/073 , Y10T29/49155 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a substrate for flip-chip connection, which uses a gold stud bump and does not have a Kirkendall void formed during reflowing with a solder bump. SOLUTION: On a printed circuit board 10, a surface of the solder bump 14 made of tin is coated with a palladium film 16 slower in diffusion speed than gold constituting the gold stud bump 24. Consequently, palladium reduces the speed of diffusion of gold of the gold stud bump into tin of the solder bump and then no Kirkendall void is formed. Consequently, internal cracking caused by a Kirkendall void is suppressed to prevent: an increase in resistance due to expansion of an internal crack during heat generation by the semiconductor chip 20; and a decrease in connection reliability due to thermal expansion of the air in the internal crack. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于倒装芯片连接的基板，其使用金柱凸起并且在用焊料凸块回流期间不形成Kirkendall空隙。解决方案：在印刷电路板10上，由锡制成的焊料凸块14的表面以比构成金柱凸块24的金的扩散速度慢的钯膜16涂覆。因此，钯降低了扩散速度金金柱的金子撞到焊锡凸块的锡中，然后没有形成Kirkendall空隙。因此，抑制由Kirkendall空隙引起的内部裂纹，以防止由于半导体芯片20的发热期间的内部裂纹膨胀而导致的电阻增加; 并且由于内部裂纹中的空气的热膨胀导致的连接可靠性降低。版权所有（C）2010，JPO＆INPIT

44. 发明专利

JPWO2006131979A1 無電解Ｎｉめっき部のはんだ付け方法有权
公开(公告)号：JPWO2006131979A1
公开(公告)日：2009-01-08
申请号：JP2007520005
申请日：2005-06-10
申请人：千住金属工業株式会社
发明人：良一倉田 , 良一倉田 , 相馬　大輔 , 大輔相馬 , 岡田　弘史 , 弘史岡田
IPC分类号： B23K1/20 , B23K1/00 , B23K1/19 , B23K35/26 , C22C13/00 , H01L21/60 , H05K3/34
CPC分类号： B23K35/262 , H05K3/244 , H05K3/3463 , H05K2201/10734 , H05K2203/072
摘要：無電解Niめっきが施されたBGAの電極を鉛フリーはんだのはんだボールではんだ付けすると、外的衝撃ではんだ付け部が容易に剥離してしまう。無電解NiめっきされたBGA電極をPが0.03〜0.1質量%添加された鉛フリーはんだではんだ付けすると、はんだ付け部に形成される脆い性質のSnNiの金属間化合物や無電解Niめっき表面のP層の成長を抑制して接合強度を向上させる。

45. 发明专利

JP2008291348A Connecting terminal, semiconductor package using connecting terminal, and method for manufacturing semiconductor package 有权
标题翻译：连接端子，使用连接端子的半导体封装以及制造半导体封装的方法
公开(公告)号：JP2008291348A
公开(公告)日：2008-12-04
申请号：JP2008097381
申请日：2008-04-03
申请人： Hitachi Chem Co Ltd , 日立化成工業株式会社
发明人： EJIRI YOSHINORI , HATAKEYAMA SHUICHI , HASEGAWA KIYOSHI
IPC分类号： C23C18/52 , C23C18/31 , C23C18/34 , C23C18/42 , H01L23/12
CPC分类号： C23C18/1651 , C23C18/1837 , C23C18/42 , C23C18/54 , H01L21/4846 , H01L21/561 , H01L23/3128 , H01L23/498 , H01L23/49816 , H01L23/49822 , H01L23/49838 , H01L23/544 , H01L24/16 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L24/97 , H01L2223/54426 , H01L2223/5446 , H01L2224/13099 , H01L2224/13111 , H01L2224/16225 , H01L2224/29111 , H01L2224/2919 , H01L2224/32057 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/49 , H01L2224/73204 , H01L2224/73265 , H01L2224/81121 , H01L2224/81801 , H01L2224/83385 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01016 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01031 , H01L2924/01032 , H01L2924/01033 , H01L2924/0104 , H01L2924/01041 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01057 , H01L2924/01061 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/01088 , H01L2924/0132 , H01L2924/01322 , H01L2924/0133 , H01L2924/014 , H01L2924/09701 , H01L2924/10329 , H01L2924/12044 , H01L2924/15311 , H01L2924/15787 , H01L2924/15788 , H01L2924/1579 , H01L2924/181 , H01L2924/351 , H05K3/244 , H05K2203/072 , H05K2203/073 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2924/20752 , H01L2924/00015 , H01L2224/05599 , H01L2224/0401
摘要： PROBLEM TO BE SOLVED: To improve connection reliability of a connecting terminal having an immersion gold plating film. SOLUTION: Each of conducting terminals 110, 111 is provided with: a conductor layer 2; an electroless nickel plating film 3; a first palladium plating film 5, i.e., an immersion or electroless palladium plating film having purity of 99 mass% or more; a second palladium plating film, i.e., an electroless palladium plating film having purity of 90 mass% or higher but less than 99 mass%; and an immersion gold plating film 6. In the connecting terminal, the electroless nickel plating film 3, the first palladium plating film 4, the second palladium plating film 5 and the immersion gold plating film 6 are laminated in this order on one side of the conductor layer 2, and the immersion gold plating layer 6 is positioned as the topmost layer on the side opposite to the conductor layer 2. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提高具有浸金镀膜的连接端子的连接可靠性。
解决方案：导电端子110,111中的每一个设置有：导体层2; 化学镀镍膜3; 第一钯镀膜5，即纯度为99质量％以上的浸渍或无电解镀钯膜; 第二钯镀膜，即纯度为90质量％以上且小于99质量％的无电镀钯膜; 和浸镀金镀膜6.在连接端子中，将化学镀镍膜3，第一镀钯膜4，第二镀钯膜5和浸镀镀金膜6依次层压在导体层2，并且浸金镀层6被定位为与导体层2相对的一侧上的最上层。版权所有（C）2009，JPO＆INPIT

46. 发明专利

JP2008285752A METHOD FOR BONDING ELECTRONIC COMPONENT FINISHED WITH ELECTROLESS NiXP FOR PREVENTING BRITTLE FRACTURE 有权
标题翻译：用电镀NiXP焊接电子元件以预防脆性碎片的方法
公开(公告)号：JP2008285752A
公开(公告)日：2008-11-27
申请号：JP2008111954
申请日：2008-04-23
申请人： Korea Advanced Inst Of Sci Technol , 韓国科学技術院Korea Advanced Institute Of Science And Technology
发明人： YU JIN , JANG DONG-MIN , JEE YOUNG-KUN
IPC分类号： C23C18/50 , B23K1/00 , B23K1/20 , B23K35/26 , B23K101/40 , C22C12/00 , C22C13/00 , C22C27/00 , C22C27/04 , C23C28/00 , H01L23/02
CPC分类号： B23K1/0016 , B23K35/262 , B23K2201/40 , H01L2224/03464 , H01L2224/0401 , H01L2224/05155 , H01L2224/05644 , H01L2224/05664 , H01L2224/131 , H01L2224/13111 , H01L2224/16 , H01L2224/16503 , H01L2924/01004 , H01L2924/01025 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H05K3/244 , H05K3/3463 , H05K2203/072 , H01L2924/00 , H01L2924/00014 , H01L2924/014
摘要： PROBLEM TO BE SOLVED: To provide a method for preventing brittle fracture occurring at a solder joint when electronic components finished with electroless Ni plating are bonded using a solder. SOLUTION: The method for preventing the brittle fracture occurring at the solder joint comprises the steps of applying electroless NiXP plating onto the electronic components to form a metal layer, wherein X is at least one kind of elements selected from among W, Mo, Co, Ti, Zr, Zn, V, Cr, Fe, Nb, Re, Mn, Tl and Cu; and reflowing a solder on the electroless NiXP layer to bond the electronic components. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种当使用焊料粘合使用化学镀Ni电镀的电子部件时，在焊接接头处发生的脆性断裂的方法。解决方案：用于防止在焊接接头处发生脆性断裂的方法包括以下步骤：在电子部件上施加化学镀NiXP以形成金属层，其中X是选自W，Mo中的至少一种元素，Co，Ti，Zr，Zn，V，Cr，Fe，Nb，Re，Mn，Tl和Cu; 并在无电镀NiXP层上回流焊料以结合电子部件。版权所有（C）2009，JPO＆INPIT

47. 发明专利

JP2007243032A Method of manufacturing wiring substrate 审中-公开
标题翻译：制造接线基板的方法
公开(公告)号：JP2007243032A
公开(公告)日：2007-09-20
申请号：JP2006065986
申请日：2006-03-10
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： FURUHATA HIDEMICHI , KIMURA SATOSHI , KANEDA TOSHIHIKO , KIJIMA TAKESHI
IPC分类号： H05K3/18
CPC分类号： H05K3/184 , C23C18/1608 , C23C18/1651 , C23C18/1692 , C23C18/1879 , C23C18/30 , C23C18/31 , C23C18/36 , H05K3/24 , H05K2203/0565 , H05K2203/072 , H05K2203/088 , H05K2203/1476
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a wiring substrate by which high-density wiring can be formed with high accuracy without using a plated resist.
SOLUTION: The method is used to manufacture a wiring substrate by a nonelectrolytic plating method which can precipitate metal without using the plated resist, and it includes a step (a) to form a catalyst layer in a specified pattern on a substrate, a step (b) to form a first metal layer by immersing the substrate in a nonelectrolytic plating liquid to precipitate metal on the catalyst layer, a step (c) to expose the upper surface of the substrate in steam, and a step (d) to form a second metal layer by immersing the substrate in the nonelectrolytic plating liquid to further precipitate metal on the first metal layer.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造可以高精度地形成高密度布线的布线基板的方法，而不使用电镀抗蚀剂。解决方案：该方法用于通过非电解电镀方法制造布线基板，该方法可以在不使用电镀抗蚀剂的情况下沉淀金属，并且包括在基板上形成规定图案的催化剂层的工序（a）步骤（b）通过将基板浸渍在非电解电镀液中以在催化剂层上沉淀金属而形成第一金属层，步骤（c）以蒸汽暴露基板的上表面，以及步骤（d）通过将基板浸入非电解电镀液中以进一步在第一金属层上沉淀金属来形成第二金属层。版权所有（C）2007，JPO＆INPIT

48. 发明专利

JP3952129B2 Semiconductor device, the mounting substrate and method of manufacturing the same, circuit board and electronic equipment 有权
公开(公告)号：JP3952129B2
公开(公告)日：2007-08-01
申请号：JP2000600305
申请日：2000-02-17
申请人：セイコーエプソン株式会社
发明人：伸晃橋元
IPC分类号： H01L23/12 , H01L21/56 , H01L21/60 , H01L23/498 , H05K1/11 , H05K3/18 , H05K3/24 , H05K3/32 , H05K3/42
CPC分类号： H01L24/86 , H01L21/563 , H01L23/498 , H01L23/49816 , H01L23/49827 , H01L23/4985 , H01L24/29 , H01L24/83 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/16237 , H01L2224/29101 , H01L2224/2919 , H01L2224/2929 , H01L2224/29299 , H01L2224/32225 , H01L2224/45144 , H01L2224/73203 , H01L2224/73204 , H01L2224/8319 , H01L2224/838 , H01L2924/00013 , H01L2924/01005 , H01L2924/01015 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/07811 , H01L2924/15184 , H01L2924/15311 , H01L2924/19041 , H01L2924/19043 , H05K1/0393 , H05K1/112 , H05K3/242 , H05K3/243 , H05K3/323 , H05K3/422 , H05K2201/0352 , H05K2201/0391 , H05K2201/0394 , H05K2203/049 , H05K2203/072 , H05K2203/0733 , H05K2203/1476 , H05K2203/1545 , H01L2924/00 , H01L2924/00014 , H01L2224/29099 , H01L2224/29199 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671
摘要： There is provided a semiconductor device comprising: a first plating layer formed on one surface of an interconnect pattern; a second plating layer formed within through holes in the interconnect pattern; a semiconductor chip electrically connected to the first plating layer; an anisotropic conductive material provided on the first plating layer; and a conductive material provided on the second plating layer, wherein the first plating layer has appropriate adhesion properties with the anisotropic conductive material, and the second plating layer has appropriate adhesion properties with the conductive material.

49. 发明专利

JP2006302972A Wiring board and manufacturing method thereof 审中-公开
标题翻译：接线板及其制造方法
公开(公告)号：JP2006302972A
公开(公告)日：2006-11-02
申请号：JP2005118799
申请日：2005-04-15
申请人： Alps Electric Co Ltd , アルプス電気株式会社
发明人： SUZUKI KUNIAKI , KUBOTA HIROSHI , HAGA NOBUAKI , MIMORI KENICHI
IPC分类号： H05K1/09 , H05K3/18
CPC分类号： H05K3/388 , H05K1/0306 , H05K3/4061 , H05K2203/072 , Y10T428/24331
摘要： PROBLEM TO BE SOLVED: To provide a wiring board on which a Cu plating layer having adhesion performance on both a ceramic layer and an Ag connection layer can be obtained, and a manufacturing method thereof. SOLUTION: One part of the ceramic layer 12 and the top surface of the Ag connection layer 14 are covered with an Ag thin-film layer 15. The Cu wiring layer 11 is formed on the ceramic layer 12 or the Ag connection layer 14 via this Ag thin-film layer 15. The Ag thin-film layer 15 contributes to improvement of connection strength between the Cu wiring layer 11 and the Ag connection layer 14 in forming the Cu wiring layer 11 by non-electrolytic plating, and formation of the Cu wiring layer 11 having a sufficient thickness on the ceramic layer 12. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决问题的方法：提供可以获得在陶瓷层和Ag连接层上具有粘合性能的Cu镀层的布线基板及其制造方法。解决方案：陶瓷层12的一部分和Ag连接层14的上表面被Ag薄膜层15覆盖。铜布线层11形成在陶瓷层12或Ag连接层通过该Ag薄膜层15，Ag薄膜层15有助于通过非电解电镀形成Cu布线层11中的Cu布线层11和Ag连接层14之间的连接强度的提高，并且形成在陶瓷层12上具有足够厚度的Cu布线层11。版权所有（C）2007，JPO＆INPIT

50. 发明专利

JP2006229031A Method of manufacturing wiring board 有权
标题翻译：制造接线板的方法
公开(公告)号：JP2006229031A
公开(公告)日：2006-08-31
申请号：JP2005042119
申请日：2005-02-18
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： SATO NAOYA , NARITA AKIHITO , AKATSUKA SATORU , ABE TSUTOMU
IPC分类号： H05K3/26 , H05K3/06 , H05K3/18
CPC分类号： H05K3/244 , H05K3/06 , H05K3/26 , H05K3/388 , H05K2201/0761 , H05K2203/072 , H05K2203/0789 , H05K2203/0793 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49155 , Y10T29/49156
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a wiring board of high reliability with high efficiency. SOLUTION: A resin board 10 is prepared where a metal layer 16 containing a first layer 12 and a second layer 14 formed on the first layer 12 is formed. A wiring pattern 20 containing the first layer 12 and the second layer 14 which are patterned is formed by etching the metal layer 16, and a part of the first layer 12 is left outside the second layer 14 of the wiring pattern 20. The wiring pattern 20 and the leftover of the first layer 12 are subjected to electroless plating. Thereafter, the resin board 10 is cleaned. The cleaning of the resin board 10 is carried out using an acid solution for dissolving and removing metal deposited on the leftover of the first layer 12 through an electroless plating process and the leftover of the first layer 12, and/or an alkaline solution for dissolving the resin board 10 to remove its part which supports the leftover of the first layer 12. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种高效率地制造高可靠性的布线基板的方法。解决方案：制备树脂板10，其中形成包含形成在第一层12上的第一层12和第二层14的金属层16。通过蚀刻金属层16形成包含图案化的第一层12和第二层14的布线图案20，并且第一层12的一部分留在布线图案20的第二层14的外侧。布线图案并且第一层12的剩余物进行无电镀。此后，清洁树脂板10。树脂板10的清洁是通过化学镀处理和第一层12的剩余部分和/或溶解的碱溶液，使用用于溶解和除去沉积在第一层12的剩余部分上的金属的酸溶液进行的树脂板10去除其支撑第一层12的剩余部分。版权所有：（C）2006，JPO＆NCIPI

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