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1. 发明专利

JP2006229031A Method of manufacturing wiring board 有权
标题翻译：制造接线板的方法
公开(公告)号：JP2006229031A
公开(公告)日：2006-08-31
申请号：JP2005042119
申请日：2005-02-18
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： SATO NAOYA , NARITA AKIHITO , AKATSUKA SATORU , ABE TSUTOMU
IPC分类号： H05K3/26 , H05K3/06 , H05K3/18
CPC分类号： H05K3/244 , H05K3/06 , H05K3/26 , H05K3/388 , H05K2201/0761 , H05K2203/072 , H05K2203/0789 , H05K2203/0793 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49155 , Y10T29/49156
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a wiring board of high reliability with high efficiency. SOLUTION: A resin board 10 is prepared where a metal layer 16 containing a first layer 12 and a second layer 14 formed on the first layer 12 is formed. A wiring pattern 20 containing the first layer 12 and the second layer 14 which are patterned is formed by etching the metal layer 16, and a part of the first layer 12 is left outside the second layer 14 of the wiring pattern 20. The wiring pattern 20 and the leftover of the first layer 12 are subjected to electroless plating. Thereafter, the resin board 10 is cleaned. The cleaning of the resin board 10 is carried out using an acid solution for dissolving and removing metal deposited on the leftover of the first layer 12 through an electroless plating process and the leftover of the first layer 12, and/or an alkaline solution for dissolving the resin board 10 to remove its part which supports the leftover of the first layer 12. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种高效率地制造高可靠性的布线基板的方法。解决方案：制备树脂板10，其中形成包含形成在第一层12上的第一层12和第二层14的金属层16。通过蚀刻金属层16形成包含图案化的第一层12和第二层14的布线图案20，并且第一层12的一部分留在布线图案20的第二层14的外侧。布线图案并且第一层12的剩余物进行无电镀。此后，清洁树脂板10。树脂板10的清洁是通过化学镀处理和第一层12的剩余部分和/或溶解的碱溶液，使用用于溶解和除去沉积在第一层12的剩余部分上的金属的酸溶液进行的树脂板10去除其支撑第一层12的剩余部分。版权所有：（C）2006，JPO＆NCIPI

2. 发明专利

JP2006032483A Manufacturing method of wiring circuit board 审中-公开
标题翻译：电路板制造方法
公开(公告)号：JP2006032483A
公开(公告)日：2006-02-02
申请号：JP2004206068
申请日：2004-07-13
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： AKATSUKA SATORU , ABE TSUTOMU , NANBA TOSHISHIGE
IPC分类号： H05K3/18 , C23C18/31 , H01L21/60 , H05K3/26
摘要： PROBLEM TO BE SOLVED: To provide a method for efficiently manufacturing a highly reliable wiring circuit board. SOLUTION: Non-electrolytic plating processing is conducted to a wiring pattern 12 provided on a base substrate 10 by utilizing a plating solution 20 including at least one of thiourea and its derivative. The base board 10 is washed using a solvent 30 including amine. Thereafter, a resist layer 40 is formed on the base board 10. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种高效制造高可靠性布线电路板的方法。解决方案：通过利用包括硫脲及其衍生物中的至少一种的电镀液20，对设置在基底基板10上的布线图案12进行非电解电镀处理。使用包括胺的溶剂30洗涤基板10。此后，在基板10上形成抗蚀剂层40.版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2007119820A Method of manufacturing wiring board, and plating apparatus 审中-公开
标题翻译：制造布线方法及镀敷装置
公开(公告)号：JP2007119820A
公开(公告)日：2007-05-17
申请号：JP2005311474
申请日：2005-10-26
申请人： Seiko Epson Corp , Yamato Denki Kogyo Kk , セイコーエプソン株式会社 , 大和電機工業株式会社
发明人： AKATSUKA SATORU , ABE TSUTOMU , NISHIZAWA MAKIO , KIYOZAWA YUICHI
IPC分类号： C25D7/00 , C25D7/06 , C25D21/12 , H05K3/18 , H05K3/24
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a wiring board by which the wiring board high in reliability can efficiently be formed while taking environment into consideration, and to provide a plating apparatus.
SOLUTION: The method of manufacturing the wiring board includes the formation of a lead-free solder layer to cover at least a part of a tin layer 24 by facing a wiring pattern 20 wherein at least a part of the surface is the tin layer 24 and an anode 42 each other in a plating bath 45, bringing cathodes arranged at both ends of the plating bath 45 into contact with the wiring pattern and electrolyzing. An interval between the wiring pattern 20 and the anode 42 is set to 0.02-0.1 m and the distance between the cathodes 44 is set to ≤2 m. The electroplating process is carried out so that the current density of current flowing in the wiring pattern 20 is 200-1,000 A/m
2 .
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造布线板的方法，通过该方法可以在考虑环境的同时有效地形成可靠性高的布线板，并提供电镀装置。解决方案：制造布线板的方法包括形成无铅焊料层，以通过面对布线图案20覆盖锡层24的至少一部分，其中表面的至少一部分是锡层24和阳极42，使镀敷槽45的两端配置的阴极与布线图形接触并进行电解。布线图案20和阳极42之间的间隔设定为0.02〜0.1μm，阴极44之间的距离设定为≤2μm。进行电镀处理，使得在布线图案20中流动的电流的电流密度为200-1,000A / m 2。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2006054418A Manufacturing method of wiring board 有权
标题翻译：接线板制造方法
公开(公告)号：JP2006054418A
公开(公告)日：2006-02-23
申请号：JP2005023605
申请日：2005-01-31
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： AKATSUKA SATORU , ABE TSUTOMU , NANBA TOSHISHIGE , SATO NAOYA , NARITA AKIHITO
IPC分类号： H05K3/26 , H05K3/18
CPC分类号： H05K3/26 , C23C18/1608 , C23C18/1689 , C23C18/52 , H05K3/244 , H05K3/386 , H05K2201/0761 , H05K2203/072 , H05K2203/0789 , H05K2203/0793
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of efficiently manufacturing a high reliable wiring board.
SOLUTION: The manufacturing method of the wiring board comprises a process of performing electroless plating treatment to a circuit pattern 12 prepared in a base substrate, and a process of cleaning the base substrate 10. The process of cleaning the base substrate 10 comprises at least one process of utilizing an alkaline solvent and an acid solvent.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种有效地制造高可靠性布线板的制造方法。解决方案：布线板的制造方法包括对在基底基板中制备的电路图案12进行无电镀处理的工艺和清洁基底基板10的工艺。清洁基底10的工艺包括至少一种利用碱性溶剂和酸溶剂的方法。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2007123425A Manufacturing method of printed circuit board 审中-公开
标题翻译：印刷电路板的制造方法
公开(公告)号：JP2007123425A
公开(公告)日：2007-05-17
申请号：JP2005311475
申请日：2005-10-26
申请人： Seiko Epson Corp , Yamato Denki Kogyo Kk , セイコーエプソン株式会社 , 大和電機工業株式会社
发明人： ABE TSUTOMU , AKATSUKA SATORU , NISHIZAWA MAKIO , KIYOZAWA YUICHI
IPC分类号： H05K3/34
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of printed circuit board that enables manufacture of a high-reliability printed circuit board.
SOLUTION: In the manufacturing method of printed circuit board, a thermosetting resin 32 is provided to a base board 10 so as to cover a part of a conductive pattern 20 formed on the base board 10. The thermosetting resin 32 is semi-cured with the first heat treatment. A plating layer 26 is formed on the exposed area extended from the thermosetting resin 32 in the conductive pattern 20 by the plating process to the conductive pattern 20. Thereafter, the thermosetting resin 32 is cured by the second heat treatment, and a resin layer 30 is formed.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供能够制造高可靠性印刷电路板的印刷电路板的制造方法。解决方案：在印刷电路板的制造方法中，将热固性树脂32设置到基板10上，以覆盖形成在基板10上的导电图案20的一部分。热固性树脂32是半用第一次热处理固化。在导电图案20中的热固性树脂32的暴露区域上通过电镀工艺形成镀层26到导电图案20.然后，热固性树脂32通过第二热处理固化，并且树脂层30 形成了。版权所有（C）2007，JPO＆INPIT

6. 发明专利

JP2006032484A Manufacturing method of wiring circuit board 审中-公开
标题翻译：电路板制造方法
公开(公告)号：JP2006032484A
公开(公告)日：2006-02-02
申请号：JP2004206069
申请日：2004-07-13
申请人： Seiko Epson Corp , セイコーエプソン株式会社
发明人： AKATSUKA SATORU , ABE TSUTOMU , NANBA TOSHISHIGE
IPC分类号： H05K3/18 , C23C18/52 , H01L21/60 , H05K3/24 , H05K3/26
摘要： PROBLEM TO BE SOLVED: To provide a method for efficiently manufacturing a highly reliable wiring board.
SOLUTION: A plated layer 15 is formed in a thickness less than 0.1 μm by conducting first non-electrolytic plating processing to a wiring pattern 12 formed on a base board 10 utilizing a plating solution 20 including at least one of thiourea and its derivative. The base board 10 is washed using a solvent 30 including amine. A resist layer 40 is formed partially covering the plated layer 15 to the base board 10. Second non-electrolytic plating processing is conducted to an area exposed from the resist layer 40 in the plated layer 15. Heating processing is not conducted between a first non-electrolytic plating process and a forming process of the resist layer 40.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种高效制造高可靠性线路板的方法。
解决方案：利用包含至少一种硫脲及其电镀液的电镀液20，通过对形成在基板10上的布线图案12进行第一非电解电镀处理，形成厚度小于0.1μm的镀层15 衍生物。使用包括胺的溶剂30洗涤基板10。将抗蚀剂层40部分地覆盖到基板10的镀层15上。对镀层15中的抗蚀剂层40露出的区域进行第二非电解电镀处理。加热处理不是在第一非 - - 电镀工艺和抗蚀剂层40的形成过程。版权所有（C）2006，JPO＆NCIPI

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