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41. 发明专利

JPS62269512A VOLTAGE COMPARATOR 失效
公开(公告)号：JPS62269512A
公开(公告)日：1987-11-24
申请号：JP11274486
申请日：1986-05-19
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： TSUKAHARA TSUNEO , AKAZAWA YUKIO
IPC分类号： H03K5/153 , H03F1/30 , H03K5/08
摘要： PURPOSE:To attain high accuracy and high speed by using a differential amplifier setting in itself the bias voltage of a load transistor (TR) so as to reduce the offset of a comparator even when a capacitance element having no voltage dependancy is not used. CONSTITUTION:Switches SW3, SW4 are closed in the preset mode with a clock theta1 at a high level and the gate and drain of load TRs MP1, MP2 are short- circuited to automatically set a bias voltage. In case, a switch SW2 is also closed and a reference voltage VREF is applied to the gate of a drive TR MN2. If unbalanced threshold voltage exists between differential TRs MN2, MN3 and MP1, MP2, the bias voltage of the TRs MP1, MP2 are set accordingly. In the amplifier mode, switches SW3,SW4 are opened and the said bias voltage is kept respectively in capacitors CGSI, CGS2. Further, the switch SW2 is opened and the switch SW1 is closed to apply an input voltage VIN to the gate of the TR MN2. In the latch mode, the input voltage difference is amplified rapidly up to the logical amplitude level. Thus, the input converted offset voltage is reduced without using a capacitance element.

42. 发明专利

JPS622490B2 失效
公开(公告)号：JPS622490B2
公开(公告)日：1987-01-20
申请号：JP10813781
申请日：1981-07-13
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： MATSUTANI YASUYUKI , AKAZAWA YUKIO , IWATA ATSUSHI
IPC分类号： H03M1/10 , H03M1/00

43. 发明专利

JPS60102011A INPUT MATCHING CIRCUIT 失效
公开(公告)号：JPS60102011A
公开(公告)日：1985-06-06
申请号：JP21036483
申请日：1983-11-08
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： ISHIHARA NOBORU , AKAZAWA YUKIO , OBARA MAMORU
IPC分类号： H03H11/28
摘要： PURPOSE:To widen the band of matching characteristics and to realize adaption to the input matching of a microwave integrated circuit by using the emitter input impedance of a transistor (TR) as the impedance for matching an amplifier circuit input. CONSTITUTION:An emitter input circuit for a TR consists of resistances 16, 17, and 20, and a TR19. When its input impedance is Rin2 and the input impedance of a TR8 is Rin1, the total input impedance is the parallel impedance of Rin1 and Rin2. The current amplification factors of both TRs are almost equalized to each other, resistances 9 and 20 are set sufficiently large, and resistances 16 and 17 have proper values. Then, Rin1>>Rin2 and the total input impedance Rin is equalized to Rin2. Consequently, matching is possible as to even a low-impedance signal source and a transmission line, and the purpose is attained.

44. 发明专利

JPS60102005A VARIABLE GAIN AMPLIFIER CIRCUIT 失效
公开(公告)号：JPS60102005A
公开(公告)日：1985-06-06
申请号：JP20968983
申请日：1983-11-08
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： ISHIHARA NOBORU , AKAZAWA YUKIO , OBARA MAMORU
IPC分类号： H03G3/10 , H03G3/02
摘要： PURPOSE:To improve output waveform distortion at the time of a low gain in an amplifier which by-passes the bias current of an amplifying transistor TR and varies in gain by inserting a diode and a resistance in series with the emitter of this TR. CONSTITUTION:A bias current is allowed by a current by-pass TR6 to by-pass an amplifying TR5. The diode D for improving waveform distortion and series feedback resistance RE are inserted in series with the emitter of the amplifying TR5. Consequently, the linear part of IC-VBE characteristics (not shown in a figure) of the amplifying TR5 is gentle and the output waveform distortion when the current IC is small, i.e. at the time of a low gain is improved. Further, peaking capacitors CP1 and CP2 are inserted in parallel to the diode D and feedback resistance RE to obtain a wide band.

45. 发明专利

JPS5810919A ANALOG-TO-DIGITAL CONVERTER 失效
公开(公告)号：JPS5810919A
公开(公告)日：1983-01-21
申请号：JP10813681
申请日：1981-07-13
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： AKAZAWA YUKIO , MATSUTANI YASUYUKI , IWATA ATSUSHI
IPC分类号： H03M1/10 , H03M1/00 , H03M1/06 , H03M1/38 , H03M1/46 , H03M1/68
摘要： PURPOSE:To improve the conversion speed with high accurcy, by providing a local DA converter. CONSTITUTION:A code where an input analog signal from a terminal 11 held at a sample holding circuit 20 and an output of a local DA converter 14 are coincident with, is generated from a comparator 15 and a sequential approxiamtion register (SAR)13 through sequential comparison. A shift code generating circuit 16 is driven with the code of an high-order corresponding to the low-order DA converter input of the local DA converter 14 out of codes obtained from the sequential comparison to generate a shift amount determined in advance and this shift amount is substracted from the code from the SAR13 obtained at the sequential comparison at a code shift circuit 21, allowing to obtain a correct output code and output from a terminal 12.

46. 发明专利

JPS561625A BINARY COUNTER 失效
公开(公告)号：JPS561625A
公开(公告)日：1981-01-09
申请号：JP7721179
申请日：1979-06-19
申请人： NIPPON ELECTRIC CO , NIPPON TELEGRAPH & TELEPHONE
发明人： MURATA MASANORI , ITOU MITSUTOSHI , AKAZAWA YUKIO , SUDOU TSUNETAKA
IPC分类号： H03K23/58 , H03K23/00
摘要： PURPOSE:To increase the working velocity by inserting the 2nd and the 3rd inverters between the output terminal of the 1st FF connected to the input terminal of the 1st inverter and the wired AND to which the output terminals of the 2nd and subsequent FFs are connected. CONSTITUTION:Inverters 6 and 7 are inserted between output terminal 5 of FF1 connected to the input terminal of inverter 4 and wired AND wiring 3 to which the output terminals of the 2nd and subsequent FFs are connected. Now the input pulse is applied through terminal 1 with repetition of ON and OFF given to each FF, and thus the counter carries out the input pulses. Then the input terminal of inverter 6 becomes low in potential when the counting proceeds with the high potential secured for the input of inverter 7, and the output terminal holds the low potential when the output terminal of FF1 becomes low in potential. And the charge is given only to the parasitic capacity accompanied to the output terminal of inverter 6 when the output terminal of FF1 features the high potential. In this way, the working velocity can be increased easily for the counter.

47. 发明专利

JPS55151840A TWOOTERMINAL SIGNAL GENERATING CIRCUIT 失效
公开(公告)号：JPS55151840A
公开(公告)日：1980-11-26
申请号：JP5967479
申请日：1979-05-17
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： NISHINO YUTAKA , AKAZAWA YUKIO , SUDOU TSUNETAKA , ITOU MITSUTOSHI
IPC分类号： H04M1/76 , H03B1/00 , H04M1/50 , H04M19/04
摘要： PURPOSE:To realize easily the various properties required by the two-terminal generating circuit and thus facilitate the easy circuit designing, by setting impedance viewed from the two external terminals in the optional way after giving the control to the impedance control circuit. CONSTITUTION:One terminal of current output type signal source 2 comprising signal generator 5 and amplifying circuit including transistor TRQ8, serial control type power circuit 3 and impedance control circuit 4 each is connected to external terminal 1a. And the other terminal of these circuit each is connected to external terminal 1b respecrively. Then the impedance viewed from terminals 1a and 1b can be set optionally by giving the control to circuit 4. Thus the requirement conditions required by the two-terminal signal generating circuit can be realized in a simple way without giving any effect to the amplifying circuit or the power circuit. And accordingly, the circuit designing can be facilitated. Among the above requirement conditions are the DC resistance, the slope of the DC characteristics, the AC impedance and the like.

48. 发明专利

JPS55135457A LSI CIRCUIT FOR TELEPHONE SET 失效
公开(公告)号：JPS55135457A
公开(公告)日：1980-10-22
申请号：JP4314479
申请日：1979-04-10
申请人： NIPPON TELEGRAPH & TELEPHONE , NIPPON ELECTRIC CO
发明人： YOSHIRI MAKOTO , NISHINO YUTAKA , AKAZAWA YUKIO , NISHIHARA KANEYUKI , HARA HIROSHI
IPC分类号： H04M1/00 , H04M1/253 , H04M1/50 , H04M19/08
摘要： PURPOSE:To realize the effective use for the current to be supplied to the telephone set, by piling up the digital circuit and analog interface circuit parts vertically and then combining the output of the D/A converter and the preamplifier input of the interface circuit via the level shift circuit. CONSTITUTION:The ground terminals of interface circuit 3 which transmits the analog signals are connected en bloc to the (+) terminal of digital circuit in the microprocessor or the like. And the (-) terminal of circuit 6 is connected to the telephone terminal (-). The power source of the level shift circuit is connected between telephone terminals (+) and (-). The current supplied to the telephone via terminals 1a and 1b flows into circuit 3 in the greater part to be consumed for the steady operation there, and then flows correctively to the power terminal of circuit 6. In this case, the steady power supply is secured for both circuits 3 and 6 since both the preamplifier of circuit 3 and the power source of circuit 6 are stabilized by constant voltage diodes 5 and 10 each.

49. 发明专利

JPH10145203A FREQUENCY/VOLTAGE-CONVERTING CIRCUIT 失效
公开(公告)号：JPH10145203A
公开(公告)日：1998-05-29
申请号：JP31687596
申请日：1996-11-14
申请人： NIPPON TELEGRAPH & TELEPHONE
发明人： KISHINE KEIJI , HIROSE MASAKI , ISHIHARA NOBORU , AKAZAWA YUKIO , SAKURAI HISAYA , KIKUSHIMA KOJI , KISHIMOTO TOMOMASA , IKEDA SATOSHI
IPC分类号： H03D3/06 , H03D3/18 , H03K9/06
摘要： PROBLEM TO BE SOLVED: To linearly frequency/voltage-convert frequency of an input signal in wider wide range by phase-comparing the output signal of a divider and the output signal of a delay circuit, extracting DC components from the output signal outputted from a phase comparator and transmitting this to a signal output terminal. SOLUTION: A 1/2 divider 2 is connected to the signal input terminal of the post-stage, and the output signal of the divider 2 is inputted to a delay circuit 3 and an EX-OR phase comparator 4. As a result, a frequency signal inputted to the input terminal 1 is converted into a half-frequency signal (two fold in period) by a dividing circuit, and this frequency signal and the delayed signal of this frequency signal are phase-compared. That is, the delay circuit 3 delays the output signal of the divider 2 which divides the input signal to be inputted to the signal input terminal, the output signal of the divider 2 and the output signal of the delay circuit 3 are phase-compared in the phase comparator 4, and a low-pass filter 5 extracts the DC components out of the output signal outputted from the phase comparator 4 and transmits this to the signal output terminal.

50. 发明专利

JPH09162807A LASER LIGHT CONTROLLER, LIGHT SIGNAL TRANSMISSION DEVICE USING LASER LIGHT CONTROLLER, PEAK DETECTION DEVICE AND LIGHT SIGNAL TRANSMISSION/RECEPTION DEVICE 失效
公开(公告)号：JPH09162807A
公开(公告)日：1997-06-20
申请号：JP32069695
申请日：1995-12-08
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： MATSUYAMA SATORU , MURAKAMI NORIO , MIKI MAKOTO , CHIBA TAKAYA , SHIMIZU KAZUYOSHI , AKAZAWA YUKIO , ISHIHARA NOBORU , NAKAMURA MAKOTO
IPC分类号： G01J11/00 , H01S5/06 , H04B10/07 , H04B10/272 , H04B10/293 , H04B10/40 , H04B10/50 , H04B10/564 , H04B10/572 , H04B10/60 , H04B10/14 , H01S3/103 , H04B10/04 , H04B10/06
摘要： PROBLEM TO BE SOLVED: To provide a laser light controller which gradually suppresses the rise of output voltage while high speed rise time is secured and which can automatically control light output by providing plural specified differential amplifiers. SOLUTION: The first differential amplifier 4-1 receives a monitor signal and a reference signal and executes a comparison amplification operation. The second differential amplifier 4-2 executes an amplification operation corresponding to a difference between a monitor-side signal and a reference-side signal and the output is outputted to a charge control element 2 as the control signal of the charge control element 2. The gain of a third differential amplifier 4-3 is set larger than the second differential amplifier 4-2, and it receives the output of the first differential amplifier 4-1 and a laser light signal and executes the comparison/amplification operation. The output is outputted to an auxiliary element for charge control 3 as the control signal of the auxiliary element for charge control 3. A charge state to a charge circuit 1 is controlled by the charge control element 2 and the charge control element 2 is controlled by the auxiliary element for charge control 3.

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