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41. 发明专利

JPS6012758A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6012758A
公开(公告)日：1985-01-23
申请号：JP15328383
申请日：1983-08-24
申请人： HITACHI LTD
发明人： TAKECHI MAKOTO , KAWAMOTO HIROSHI
IPC分类号： H01L27/10 , H01L21/8234 , H01L21/8242 , H01L27/06 , H01L27/108 , H01L29/78
摘要： PURPOSE:To enhance the flexibility of wiring design and improve the integration degree by a method wherein the polycrystalline Si wiring layer of the first layer is simultaneously formed when a polycrystalline Si gate electrode layer constituting an MOS transistor is formed, the surface layer part of the wiring layer being changed into an SiO2 by heat treatment, and the wiring layer of the second layer then being provided thereon. CONSTITUTION:A thick field SiO2 film 2 is formed in the periphery of a P type Si substrate 1 with a P type region 3 for preventing the generation of a parastic MOS underlying the film the N type source 4 and drain 5 regions are diffusion-formed in the substrate 1 therebetween. Next, the gate electrode 7 made of polycrystalline Si is formed between these regions, and at the same time the wiring layers 9 and 10 of the first layer of polycrystalline Si are formed via thin SiO2 film 11. Thereafter, heat treatment is carried out, and the electrode 7 is surrounded with a gate insulation film made of an SiO2 film 6 generated. At the same time, the surface layer parts of the wirings layers 9 and 10 are changed into the SiO2 film 12 serving as the interlayer insulation film. Thus, the film 2 with no pin holes is obtained, and the wiring layer 13 of the second layer is connected to the film via aperture.

42. 发明专利

JPS59197153A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS59197153A
公开(公告)日：1984-11-08
申请号：JP4912584
申请日：1984-03-16
申请人： Hitachi Ltd
发明人： TAKECHI MAKOTO
IPC分类号： H01L29/78 , H01L21/28 , H01L21/768 , H01L23/522
摘要： PURPOSE:To increase the degree of freedom of an Al wiring, and to obtain an IC of high density by forming a conductive layer of a predetermined shape on a gate insulating film, coating the conductive layer with an insulating film, removing one part of the insulating film and forming a semiconductor layer of a conduction type reverse to a substrate while being adjoined to the exposed conductive layer section. CONSTITUTION:A thick field oxide film 2 is formed to the peripheral section of a p type Si substrate 1 while using a p type buried layer 10 as an underlay, the upper section of the substrate 1 surrounded by the oxide film 2 is coated with a thin first gate oxide film 3, and a first polycrystalline Si layer 4 is deposited on the whole surface containing the oxide film 3. The layer 4 and the film 3 are removed selectively, a second gate oxide film 5 is applied extending over the surface of the exposed substrate 1 from the upper section of the residual layer 4, a through-hole TH is bored to the film 5, and an n type region 6 as a source or a drain is diffused and formed to the surface layer section of the exposed substrate 1. A second polycrystalline Si layer 9 being in contact with the region 6 is deposited on the whole surface and formed to a predetermined shape, a PSG film 11 is applied and a contact hole is bored, and an Al electrode 12 being in contact with the layer 9 is attached.
摘要翻译：目的：为了增加Al布线的自由度，并且通过在栅极绝缘膜上形成预定形状的导电层来获得高密度的IC，用绝缘膜涂覆导电层，除去一部分绝缘膜，并且在与暴露的导电层部分相邻的同时形成与衬底相反的导电类型的半导体层。构成：使用ap +型掩埋层10作为衬底，在ap型Si衬底1的周边部分形成厚场氧化膜2，被氧化物膜2包围的衬底1的上部被涂覆薄的第一栅极氧化膜3和第一多晶Si层4沉积在包含氧化物膜3的整个表面上。层4和膜3被选择性地去除，第二栅极氧化物膜5被涂覆在表面上暴露的基板1从残留层4的上部开始，通孔TH被填充到膜5，并且作为源极或漏极的n +型区域6扩散并形成到表面层暴露的基板1的一部分。与区域6接触的第二多晶Si层9沉积在整个表面上并形成预定的形状，施加PSG膜11并且接触孔被钻孔，并且Al电极 12与层9接触是attac HED。

43. 发明专利

JPS59135745A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS59135745A
公开(公告)日：1984-08-04
申请号：JP871683
申请日：1983-01-24
申请人： Hitachi Ltd
发明人： TAKECHI MAKOTO , IKUZAKI KUNIHIKO
IPC分类号： H01L21/822 , H01L21/82 , H01L21/8238 , H01L27/04 , H01L27/092 , H01L27/118
CPC分类号： H01L27/11807
摘要： PURPOSE:To form a delay element by a method wherein a resistor is provided on the current route of an inverter circuit. CONSTITUTION:The fundamental cell 3 such as LSI and the like has an CMOS structure which will be formed by an N type region 6 and a P type region 7. Polycrystalline silicon layers 8, 9 and 10 are formed on a substrate, the polycrystalline silicon layers 8 and 10 are used as a gate electrode and they form MOSFETs Q1, Q2, Q3 and Q4 together with the N type region 6 and the P type region 7. The drains of the MOSFETs Q1 and Q2 are connected common by a wiring 17, they constitute the first inverter 9, and their output is applied to the gate electrodes of the MOSFETs Q3 and Q4 which constitutes the second inverter through the intermediaries of the wiring 17, a wiring 18, the polycrystalline layer 9 and a wiring 19. As the resistance value of the polycrystalline silicon layer 9 is relatively high and it is inserted to the gate capacitance charging and discharging route of the second inverter as a resistor, the transfer of signals can be delayed.
摘要翻译：目的：通过在逆变器电路的当前路径上设置电阻器的方法形成延迟元件。构成：诸如LSI等的基电池3具有将由N型区域6和P型区域7形成的CMOS结构。多晶硅层8,9和10形成在基板上，多晶硅层8和10用作栅电极，并且它们与N型区域6和P型区域7一起形成MOSFET Q1，Q2，Q3和Q4。MOSFET Q1和Q2的漏极由布线17共同连接，它们构成第一反相器9，并且它们的输出通过布线17，布线18，多晶层9和布线19的中间部分施加到构成第二反相器的MOSFET Q3和Q4的栅电极。多晶硅层9的电阻值相对较高，并且作为电阻被插入到第二反相器的栅极电容充放电路径中，可以延迟信号的传送。

44. 发明专利

JPS59135744A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路设备
公开(公告)号：JPS59135744A
公开(公告)日：1984-08-04
申请号：JP871583
申请日：1983-01-24
申请人： Hitachi Ltd
发明人： TAKECHI MAKOTO
IPC分类号： H01L21/822 , H01L21/3205 , H01L21/82 , H01L21/8238 , H01L23/52 , H01L27/04 , H01L27/08 , H01L27/092 , H01L27/118
CPC分类号： H01L27/11807
摘要： PURPOSE:To prevent the decrease in working speed of the titled device by a method wherein, in the case of the LSI or VLSI of master slice system, the wiring between fundamental cells is formed using a low resistance wiring material. CONSTITUTION:In the LSI or VLSI of master slice where a fundamental cell is formed using a CMOS, the fundamental cell 3 to be formed on a semiconductor substrate has an N type region 7, a P type region 8 and gate electrodes 9, 10 and 11 formed in Y-direction with a polycrystalline silicon. Wirings 14, 15, 18, 19 and 20 are formed in X-direction as the second layer on the gate electrodes 9, 10 and 11 using the low resistance material such as aluminum and the like through the intermediary of an interlayer insulating film. The wiring 14 is connected to the source voltage, and the wiring 15 is grounded, and the wirings 18, 19 and 20 are provided for the purpose of transmission of the signal between fundamental cells. A wiring 21 is formed in Y-direction on the wirings 14, 15, 18, 19 and 20 as the third layer using a low resistance material through the intermediary of an interlayer insulating film, and it is connected to the gate electrode 9 and the wirings 19 and 20 using a through hole.
摘要翻译：目的：为了防止标题设备的工作速度降低，其中在主切片系统的LSI或VLSI的情况下，使用低电阻布线材料形成基底单元之间的布线。构成：在使用CMOS形成基电池的主片的LSI或VLSI中，要形成在半导体衬底上的基本单元3具有N型区域7，P型区域8和栅电极9,10以及 11在Y方向上形成多晶硅。通过中间层间绝缘膜，使用诸如铝等的低电阻材料，在栅极电极9,10和11上在X方向上形成布线14,15,18,19和20作为第二层。布线14与源极电压连接，布线15接地，并且布线18,19和20被设置用于在基本单元之间传输信号。在作为第三层的布线14,15,18,19,20在Y方向上通过层间绝缘膜使用低电阻材料形成布线21，并且连接到栅电极9和布线19和20使用通孔。

45. 发明专利

JPS5956761A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS5956761A
公开(公告)日：1984-04-02
申请号：JP15328183
申请日：1983-08-24
申请人： Hitachi Ltd
发明人： TAKECHI MAKOTO , KAWAMOTO HIROSHI
IPC分类号： H01L27/10 , H01L21/8234 , H01L21/8242 , H01L23/522 , H01L27/06 , H01L27/108 , H01L29/78
CPC分类号： H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： PURPOSE:To contrive to improve the flexibility of wiring design and the integration degree by a method wherein the second wiring layer is enabled to be easily connected directly to a source layer and a drain layer by thinning the film thickness of an interlayer insulation film. CONSTITUTION:Si oxide films 2 are formed on a P type Si substrate 1, and P type Si layers 3 are formed thereunder. The source layer 4 and the drain layer 5 are formed by the selective diffusion of an N type impurity. A polycrystalline Si layer 7, a gate electrode, covered with an Si thermal oxide 6 over the entire region of the outer peripheral surface is arranged on the surface of the substrate 1 therebetween, and thus an Si gate MOS transistor 8 is formed. Polycrystalline Si layers 9 and 10, the first wiring layer, are formed on the upper surface of the Si oxide films 2. A polycrystaline Si layer 13 serving as the second wiring layer is formed on an Si thermal oxide film 12. The surface worked in such a manner is coated with a phospho-silicate glass layer 15.
摘要翻译：目的：为了通过使层间绝缘膜的膜厚变薄，能够容易地将第二布线层直接连接到源极层和漏极层的方法来提高布线设计的灵活性和集成度。构成：在P型Si衬底1上形成Si氧化膜2，在其上形成P +型Si层3。源极层4和漏极层5由N +型杂质的选择性扩散形成。在其外表面的整个区域上覆盖有Si热氧化物6的多晶硅层7，栅极电极布置在其之间，由此形成Si栅极MOS晶体管8。在Si氧化膜2的上表面上形成多晶硅层9和10，第一布线层。在Si热氧化膜12上形成用作第二布线层的多晶Si层13。这种方式涂覆有磷硅酸盐玻璃层15。

46. 发明专利

JPS5851538A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS5851538A
公开(公告)日：1983-03-26
申请号：JP14946381
申请日：1981-09-24
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TAKAHASHI YOSHIKAZU , TAKECHI MAKOTO
IPC分类号： H01L21/822 , H01L21/3205 , H01L21/82 , H01L23/52 , H01L27/04 , H01L27/118
摘要： PURPOSE:To enable to facilitate the addition of wirings in a semiconductor integrated circuit device by forming a conductive layer which extends directly under upper layer wirings forming power source reinforcing lines and using the layer as wirings, thereby increasing the number of wiring channels. CONSTITUTION:A plurality of polysilicon wirings 13, 14 are respectively formed in the same directions (perpendicular to each cell row) directly under power source reinforcing lines 5, 6, and are suitably connected at the prescribed positions to the first layer aluminum wirings 15 of a wiring channel region 4. In this manner, it becomes equivalent to the increase in the number of the second layer aluminum wirings in the amount corresponding to the wirings 13, 14. Accordingly, the number of logic gates can be increased by increasing the number of wirings in the direction perpendicular to the cell row and increasing the number of wirings running in the wiring channel region.

47. 发明专利

JPS57211247A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS57211247A
公开(公告)日：1982-12-25
申请号：JP9526981
申请日：1981-06-22
申请人： HITACHI LTD
发明人： TAKECHI MAKOTO
IPC分类号： H01L21/822 , H01L21/3205 , H01L21/82 , H01L23/52 , H01L27/04 , H01L27/118 , H01L29/78
摘要： PURPOSE:To remove a restraint in regard to arrangement of an upper layer wiring of a semiconductor integrated circuit device by a method wherein the end parts of gate electrodes (especially dummy electrodes) under the bending region of the upper layer wiring are led out upward in a unit cell, and are used as the wiring extending in the direction of the upper layer wiring as they are. CONSTITUTION:The unit cell 2 is consisting of two CMOSFET's, gate electrodes Pa-Pg are extended in parallel, and a wiring Al 2b out of the second layer wirings Al 2 is bent at a right angle on a field oxide film 5 between a PMOS and an NMOS on the cell 2. At this case, the gate electrodes Pe, Pd are not used as the gate electrode, and are led out in the same direction with the wirings Al 2 by wirings Al1m, Al2e, All through penetrating holes at both the ends to be used as the equal wirings with the wirngs Al 2 as they are. Because the wirings thereof can be performed in the same direction with the wirings Al 2 even in the bending region of the wiring Al 2b, generation of complexity in the wiring can be obstructed, and because the area of the wiring region of the wirings Al 2 can be reduced, the degree of integration of the IC is enganced.

48. 发明专利

JPS5571065A CCD MEMORY SENSE AMPLIFIER 失效
公开(公告)号：JPS5571065A
公开(公告)日：1980-05-28
申请号：JP14416878
申请日：1978-11-24
申请人： HITACHI LTD
发明人： TAKECHI MAKOTO
IPC分类号： G11C11/419 , G11C27/04 , H01L21/339 , H01L29/762 , H01L29/768
摘要： PURPOSE:To prevent information breakdown at the time of read-out by impressing a voltage with which to bias a sense node reversely on the reference voltage side of a sense amplifier in a CCD memory sense amplifier impressing an output of the sense node to the gate of a differential MISFET. CONSTITUTION:A voltage Vr that the potential of a sense node 3 of CCD resistor will not be lower than the potential under an output gate of the CCD resistor is used for a power source on the reference voltage side of a sense amplifier. The sense node is thus at bias voltage Vr and even if there occurs a potential drop at the sense node due to storage charge, information breakdown can be prevented regardless of the charge being swept away. Since a read-out voltage is impressed directly on the gate of MISFET Q1, Q2, sensitivity is improved and design is facilitated.

49. 发明专利

JPS5440580A WIRING CONTACT STRUCTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS5440580A
公开(公告)日：1979-03-30
申请号：JP10658877
申请日：1977-09-07
申请人： HITACHI LTD
发明人： TAKECHI MAKOTO
IPC分类号： H01L29/78 , H01L21/28 , H01L21/768 , H01L23/522 , H01L29/43
摘要： PURPOSE:To increase the number of degrees of freedom of Al wiring formation, and to improve the degree of integration by interposing the 1st and 2nd polycrystal layers between source and drain regions formed inside a semiconductor substrateat the time of adhering an Al wiring to the both.

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