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41. 发明专利

JPS648634A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS648634A
公开(公告)日：1989-01-12
申请号：JP16231687
申请日：1987-07-01
申请人： HITACHI LTD
发明人： KASHU NOBUYOSHI , GOSHIMA HIDEKAZU , OYU SHIZUNORI , SUZUKI TADASHI
IPC分类号： H01L21/322 , H01L21/74 , H01L21/8249 , H01L27/06
摘要： PURPOSE:To form an embedded doped layer having preferable bonding characteristics by containing a polycrystalline silicon layer or a high melting point metal silicide layer at least in part of an embedded impurity-doped layer. CONSTITUTION:When oxygen ions are implanted 1X10 /cm with 1MeV of energy to a P-type single crystalline silicon substrate 1 and heat treated at 1100 deg.C by lamp annealing of fast temperature rising velocity for 60 sec, a polycrystalline silicon layer 2 having 0.5mum of width is formed at a position of approx. 2mum of depth as a center, and its both sides are formed in single crystalline silicons having no crystal defect. Then, after arsenic acid ions are implanted 5X10 /cm with 3MeV of energy, it is heat treated at 1000 deg.C for 10 min. Thereafter, an N-type doped layers 3 having junctions at positions of 0.2mum from both outsides of a polycrystalline silicon layer. A dislocation which crosses the junction is not observed at this time. If the polycrystalline silicon is not formed, arsenic ions are implanted and heat treated, dislocations 4 of high density occurs in the layer 3, and part of the dislocations 4 exists across the junction.

42. 发明专利

JPS6399546A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6399546A
公开(公告)日：1988-04-30
申请号：JP24422086
申请日：1986-10-16
申请人： HITACHI LTD
发明人： IIJIMA SHINPEI , OYU SHIZUNORI , YAMAMOTO NAOKI , HAYASHIDA TETSUYA
IPC分类号： H01L21/3205
摘要： PURPOSE:To improve the reliability of wiring and to make it possible to form an multilayer interconnection, when a metallic wiring layer is formed on a substrate having contact holes and steps, by heating and fusing the metallic wiring layer, which is deposited and formed on the substrate. CONSTITUTION:The surface of a substrate 10 is cleaned with diluted fuoric acid and the like. Then a titanium nitride (TiN) film 70 having a thickness of 0.1 mum is deposited and formed by a sputtering method using Argon (Ar). Then, an Al film 80 having a thickness of 1mum is deposited on the TiN film 70 by a sputtering method using the same Ar. At the depositing and forming step of the Al film 80, the thickness of the Al film is very thin in contact holes 40 and 50. The thickness at a step part 60 is considerably thin. Said Al film undergoes heat treatment so that it is fused and made to flow. Then the insides of the contact holes are completely filled with the Al and the step part is eliminated. The flatness of the Al film 80 is strikingly improved. Thus wire breakdown is prevented, and the increase in electric resistance can be reduced.

43. 发明专利

JPS632312A MANUFACTURE OF SINGLE CRYSTAL THIN FILM 失效
公开(公告)号：JPS632312A
公开(公告)日：1988-01-07
申请号：JP14485586
申请日：1986-06-23
申请人： HITACHI LTD
发明人： MADOKORO YUICHI , WADA YASUO , TAMURA MASAO , KETSUSAKO MITSUNORI , MIYAO MASANOBU , KASHU NOBUYOSHI , OYU SHIZUNORI , YADORI SHOJI , SHIGENIWA MASAHIRO , MURAKAMI HIDEKAZU , SUZUKI TADASHI
IPC分类号： H01L21/20 , C30B1/02 , C30B29/06 , H01L21/324
摘要： PURPOSE:To form a single crystal silicon thin film having extremely low electric impurity density on an amorphous insulating substance by covering it with one or more P-type and N-type amorphous or polycrystalline thin films including impurities substantially in equal quantity to form the single crystal thin film. CONSTITUTION:After a single crystal silicon substrate 1 and an insulating film 2 covered in desired parts on the substrate are covered continuously with a polycrystalline or amorphous silicon thin film 3 by vacuum depositing, phosphorus ions are implanted to form the film in an N-type. Further, after a polycrystalline or amorphous silicon film 4 is deposited, boron ions are implanted to form it in a P-type. In this case, the total amount of the phosphorus and the boron in the films 3, 4 is adjusted to be substantially equal. The amorphous or polycrystalline layer is single-crystallized from the exposed part of the substrate by solid phase epitaxy, and then N-and P-type impurities are diffused by annealing. Or, it is once melted by a laser to be mixed homogeneously to reduce an electric impurity density in the thin film.

44. 发明专利

JPS62249416A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62249416A
公开(公告)日：1987-10-30
申请号：JP9213886
申请日：1986-04-23
申请人： HITACHI LTD
发明人： OYU SHIZUNORI , KASHU NOBUYOSHI , SUZUKI TADASHI , WADA YASUO
IPC分类号： H01L29/73 , H01L21/28 , H01L21/331 , H01L29/72 , H01L29/78
摘要： PURPOSE:To reduce an undercut at a semiconductor substrate of its junction area by using a phenomenon where a titanic silicide film deposited on the substrate is heat-treated in a nitrogen atmosphere and is changed into a structure of nitriding titanic film/silicon film or nitriding titanic film/titanic silicide film/ silicon film. CONSTITUTION:A titanic silicide film 3 is deposited to a substrate having an insulating film 2 processed on a surface of semiconductor substrate 1. Then, once its film is heat-treated in a nitrogen atmosphere or in an atmosphere containing nitrogen, a nitriding titanic film 4 is formed on a surface side of its film 3 and silicon films 5 and 6 are formed at a substrate side. And when such heat treatment added again makes the titanic silicide film 3 nitrified wholly, the nitriding titanic film 4 is formed on the surface side of its film 3 and the silicon films 5 and 6 are formed at the substrate side. Thus, a multilayer structure comprising nitriding titanium, titanic silicide, and silicon can be formed on the substrate by utilizing a nitriding phenomenon of the titanic silicide film and shallowing of a junction in the semiconductor substrate as well as lowering the resistance of the junction and an electrode area can be simultaneously performed.

45. 发明专利

JPS62239524A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62239524A
公开(公告)日：1987-10-20
申请号：JP8203586
申请日：1986-04-11
申请人： HITACHI LTD
发明人： WADA YASUO , TAMURA MASAO , KASHU NOBUYOSHI , OYU SHIZUNORI , SUZUKI TADASHI
IPC分类号： H01L21/265 , H01L21/76
摘要： PURPOSE:To form an ion implanting layer easily on the sidewall part of grooves by a method wherein, to form an element isolating region, isolating grooves are previously filled with ion scattering material. CONSTITUTION:Grooves 16 are formed in a silicon substrate 11 and then the grooves 16 are filled with amorphous material 17 to be scattered with ion beams. First, the material 17 is implanted with ion beams to be scattered with the implanted ion beams in the lateral direction forming an impurity leading-in layer 19 on the side of grooves 16. Second, the amorphous material 17 is re moved. Third, the grooves 16 are filled with the SiO2 19 for isolating element. Through these procedures, the grooves 16 are implanted with ion beam scatter ing material 17 so that the impurity doping layer 19 may be formed easily on the sidewall part of grooves 16.

46. 发明专利

JPS62122227A METHOD FOR EVALUATION OF IMPURITY DOPED LAYER 失效
公开(公告)号：JPS62122227A
公开(公告)日：1987-06-03
申请号：JP26111485
申请日：1985-11-22
申请人： HITACHI LTD
发明人： SUZUKI TADASHI , KASHU NOBUYOSHI , OYU SHIZUNORI , WADA YASUO
IPC分类号： H01L21/66 , G01N27/00 , H01L21/265
摘要： PURPOSE:To make it possible to evaluate an impurity doped layer formed by use of high-energy ion implantation easily and accurately by forming a layer made of the material which enables it to selectively remove only that layer easily on a substrate of a semiconductor device. CONSTITUTION:On a substrate 12, a film 1 made of the material which can be removed selectively and easily is formed and after high-energy ion implantation into that substrate, only the upper layer is selectively removed by etching. For that, a conventional method can be applied to the evaluation of an impurity layer. In this case, the thickness of a deposited layer can be determined on the basis of the LSS theory. For example, when B (boron) is implanted is Si(silicon) with 1 MeV energy, a projection range Rp is 1.76mum and a standard deviation DELTARp is 0.136mum. A range within which an impurity concentration (CI) is seemed to be significant is + or -3DELTARp. Accordingly, it becomes enough to remove 1.35mum of Si. By converting this by an inhibition performance of the material of the deposited layer, the thickness of the deposited layer can be obtained.

47. 发明专利

JPS61269305A SEMICONDUCTOR MANUFACTURING EQUIPMENT 失效
公开(公告)号：JPS61269305A
公开(公告)日：1986-11-28
申请号：JP11036885
申请日：1985-05-24
申请人： HITACHI LTD
发明人： TAMURA MASAO , KASHU NOBUYOSHI , OYU SHIZUNORI , YADORI SHOJI , SUZUKI TADASHI
IPC分类号： H01L21/205 , H01L21/263 , H01L21/31
摘要： PURPOSE:To prevent the deposition of reaction products on a window surface through which light is introduced, by making a probe table 10 movable in upward and downward direction sin a photo CVD equipment. CONSTITUTION:In a photo CVD equipment, a probe table 10 is formed movable in upward and downward directions. After the probe table 10 is lowered below the height of the window 7, the specified laser light is introduced into the equipment through the window 7 again. Introducing the gas capable of removing the material deposited on the window into the equipment allows the material deposited on the windows 7, 7', and 7'' to be etched, thereby preventing the reaction products being laminated on the internal surface of the windows 7, 7', and 7'' through which light is introduced.

48. 发明专利

JPS61256553A ION-BEAM GENERATOR 失效
公开(公告)号：JPS61256553A
公开(公告)日：1986-11-14
申请号：JP9776385
申请日：1985-05-10
申请人： HITACHI LTD
发明人： SUZUKI TADASHI , TAMURA MASAO , YADORI SHOJI , WADA YASUO , KASHU NOBUYOSHI , OYU SHIZUNORI , SHINTANI AKIRA , OKUDAIRA HIDEKAZU
IPC分类号： H01J37/317 , H01J37/08 , H01L21/265
摘要： PURPOSE:To improve efficiency, with a scanning electric field independent of an acceleration voltage, by making composition in which a generator of focusing ion beams capable of being scanned, with a high acceleration voltage, is positioned before a beam-scanning part. CONSTITUTION:Ion beams 1 from an ion source 2 are made to pass through condenser lenses 3 and a mass-separator 4, and thereafter being scanned at a beam scanning part 5. Then, they are accelerated to have high energy, and focussed by object lenses 7, and the necessary amount of them are shot into an assigned position on a substrate 8 to shoot ions into, to form an ion-beam generator used in the production of a semiconductor device or the like. A transverse scanning electric field is made to be decided independent of a final acceleration voltage. Therefore, with the scanning electric field being reduced to improve efficiency, high-energy focussing ion beams of good quality, capable of being scanned, can be obtained.

49. 发明专利

JP2009176808A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2009176808A
公开(公告)日：2009-08-06
申请号：JP2008011387
申请日：2008-01-22
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： OYU SHIZUNORI , OKONOGI KENSUKE , SHIMA AKIO
IPC分类号： H01L21/265 , H01L29/78
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/268 , H01L29/1083 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which is not limited by the concentration of a diffusion layer and of which junction leak current is reduced enough.
SOLUTION: The method of manufacturing a semiconductor device includes: a step to dope an area of first conductivity type of a silicon substrate with impurities of second conductivity type opposite to first conductivity type and heat it so as to form a diffusion layer of the second conductivity type; and a step to implant nitride or fluorine ions to the diffusion layer and give a carbon dioxide gas laser to the diffusion layer.
COPYRIGHT: (C)2009,JPO&INPIT

50. 发明专利

JP2004087757A Semiconductor device and its manufacturing method 有权
公开(公告)号：JP2004087757A
公开(公告)日：2004-03-18
申请号：JP2002246287
申请日：2002-08-27
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： YAMADA SATORU , NAGAI AKIRA , OYU SHIZUNORI , NAKAMURA RYOICHI , TAKAURA NORIKATSU
IPC分类号： H01L27/092 , H01L21/28 , H01L21/8238 , H01L21/8242 , H01L27/108 , H01L29/49 , H01L29/78
CPC分类号： H01L27/10891 , H01L21/28061 , H01L21/823842 , H01L27/10894 , H01L27/10897 , H01L29/4941 , H01L29/7833
摘要： PROBLEM TO BE SOLVED: To provide a transistor, special to a DRAM (dynamic random access memory) for simultaneously achieving three points of improvement of the performance of a PMOS (p-channel metal oxide semiconductor) in the circumferential circuit of the DRAM, the reduction of a word line resistance and the mitigation of junction field of a memory cell.
SOLUTION: In the semiconductor device of a gate electrode structure consisting of three levels or more of Fermi level polysilicon, P-type polysilicon having the lowest Fermi level is arranged in a first N-type surface channel MOS (metal-oxide-semiconductor) transistor 13, N-type polysilicon having the highest Fermi level, is arranged in a second N-type surface channel MOS transistor 12 and the N-type polysilicon, having an intermediate Fermi level and produced through doping both of N-type impurities and P-type impurities, is arranged in a P-channel MOS transistor 11 respectively.
COPYRIGHT: (C)2004,JPO

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