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31. 发明专利

JPH0372670A THREE-DIMENSIONAL MEMORY ELEMENT AND ITS WRITING-READING METHOD 失效
公开(公告)号：JPH0372670A
公开(公告)日：1991-03-27
申请号：JP20881689
申请日：1989-08-11
申请人： OLYMPUS OPTICAL CO
发明人： NAKANO HIROSHI , IMAI MASAHARU , MORIMOTO MASAMICHI , FUJII MASAYUKI , NAKAMURA JUNICHI , NAKAMURA TSUTOMU
IPC分类号： G11C11/38 , H01L27/00 , H01L27/10 , H01L27/28 , H01L51/05
摘要： PURPOSE:To increase storage capacity by transferring charge without wiring each conducting layer, simplifying element structure, and enabling high degree integration, by a method wherein each threshold voltage for tunnel conduction of electric charge in each tunnel switch film is gradually increased from the 10 electrode side toward the lamination direction of a laminated body. CONSTITUTION:Each of the tunnel switch films 32a-32d is made of same material. The tunnel switch film 32a in contact with an I/O electrode 31a is the thinnest. In accordance with the distance of the film from the I/O electrode 31a, the film thickness is increased. That is, as to the tunnel switch films 32a-32d, the threshold voltage for tunnel conduction of charge is set so as to become higher as the interval between the film and the I/O electrode 31a becomes larger. A writing pulse is applied to the charge input terminal 35 of a writing circuit 33. A reading circuit 34 is constituted of a reading pulse applying terminal 36, a reading capacitor Cd in which read charge is stored, and a charge reading terminal 37.

32. 发明专利

JPS586587A MEMORY CELL 失效
公开(公告)号：JPS586587A
公开(公告)日：1983-01-14
申请号：JP6484982
申请日：1982-04-20
申请人： IBM
发明人： SHIYASHI DAARU MARABIYA
IPC分类号： G11C11/41 , G11C11/38

33. 发明专利

JP3950179B2 Tunnel diode 失效
公开(公告)号：JP3950179B2
公开(公告)日：2007-07-25
申请号：JP30643494
申请日：1994-12-09
申请人：コーニンクレッカフィリップスエレクトロニクスエヌヴィ
发明人：ウイルヘルムスマリアブロムパウルス , ペトルスカロルスミカエルクレインマルセリヌス , マルチンウォルフロナルド
IPC分类号： H01L29/88 , G11C11/22 , G11C11/38 , G11C11/56 , H01L27/115 , H01L29/08 , H01L29/51 , H01L45/00
CPC分类号： H01L29/88 , G11C11/22 , G11C11/38 , G11C11/5657 , H01L27/115 , H01L29/0895 , H01L29/51 , H01L45/00
摘要： The invention relates to a tunnel diode provided with two metallically conducting electrodes (1, 2) with an insulating dielectric (3) in between, which forms a barrier with a barrier level for electrons and which has a thickness such that electrons can tunnel through the barrier from the one to the other electrode. Such a tunnel diode has the disadvantage that it has no memory. In many applications it is desirable for the tunnel diode to hold a certain switching state, such as open/closed. According to the invention, the tunnel diode is characterized in that the dielectric (3) comprises a layer of a material which is ferroelectric at room temperature with a remanent polarization which influences the barrier level. It is achieved thereby that the tunnel diode has various switching states in dependence on the remanent polarization of the dielectric (3). The switching state is maintained until the polarization of the dielectric (3) changes.

34. 发明专利

JP3884536B2 Memory cell 失效
公开(公告)号：JP3884536B2
公开(公告)日：2007-02-21
申请号：JP21111197
申请日：1997-07-01
申请人：テキサスインスツルメンツインコーポレイテツド
发明人：ピー．バンデルワグトジャン
IPC分类号： G11C11/38 , G11C11/36
CPC分类号： B82Y10/00 , G11C11/36 , G11C2211/5614

35. 发明专利

JP2003069417A Semiconductor device and its drive method 审中-公开
标题翻译：半导体器件及其驱动方法
公开(公告)号：JP2003069417A
公开(公告)日：2003-03-07
申请号：JP2001252754
申请日：2001-08-23
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： SORADA HARUYUKI , MORIMOTO TADASHI , MORITA KIYOYUKI
IPC分类号： G11C11/38 , H01L27/10 , H03K19/0944
CPC分类号： G11C2211/5614
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device acting like a memory cell employing a negative resistive element operated at a high-speed even under a low voltage and to provide its drive method.
SOLUTION: The semiconductor device includes a series connection comprising two IBTDs 12, 13 and a DTMOS whose source electrode is connected to a memory node 17 between the IBTDs 12 and 13 and whose drain electrode is connected to a bit line 15. Since the gate and the body region of the DTMOS for controlling data input output are connected to a word line 16, even when a gate voltage of the DTMOS is low at data input output, the drain current is increased more than that of a conventional semiconductor device to deliver data at a higher speed.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种半导体器件，其作用就像使用即使在低电压下高速工作的负电阻元件的存储单元，并提供其驱动方法。解决方案：半导体器件包括串联连接，其包括两个IBTD 12,13和一个DTMOS，其源电极连接到IBTD12和13之间的存储器节点17，其漏电极连接到位线15.由于门和用于控制数据输入输出的DTMOS的主体区域连接到字线16，即使在数据输入输出端的DTMOS的栅极电压低时，漏极电流比传统半导体器件的栅极电压增加更多，以传送数据以更高的速度。

36. 发明专利

JP2002216482A SEMICONDUCTOR MEMORY INTEGRATED CIRCUIT 审中-公开
公开(公告)号：JP2002216482A
公开(公告)日：2002-08-02
申请号：JP2001289888
申请日：2001-09-21
申请人： TOSHIBA CORP
发明人： IWATA YOSHIHISA
IPC分类号： G11C11/14 , G11C11/15 , G11C11/38 , G11C11/419 , G11C13/00 , G11C16/06 , G11C17/18 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L43/08
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory integrated circuit in which sufficient read-out margin can be obtained by suppressing stress of a current driving type memory cell. SOLUTION: A MTJ-MRAM cell consisting of MTJ and a selection switch transistor QS is used for a memory cell MC. A sense amplifier SA connected to a bit line BL to which data of the memory cell MC are read out is constituted by using an operation amplifier OP. An inverse input terminal of the operation amplifier OP is connected to the bit line BL, and a fixed potential VC is given to a non-inverse input terminal. A drain and a gate of a PMOS transistor Q31 for a clamp used as a current source for charging a bit line are connected to the inverse input terminal of the operation amplifier OP, and a source is feedback-controlled by an output of the operation amplifier OP. Thereby, a clamp potential of the bit line BL is fixed to VC.

37. 发明专利

JP3275216B2 失效
公开(公告)号：JP3275216B2
公开(公告)日：2002-04-15
申请号：JP14586293
申请日：1993-06-17
IPC分类号： G11C11/22 , G11C11/36 , G11C11/38 , G11C14/00 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L29/12 , H01L29/788 , H01L29/792 , H01L29/88 , H01L39/02

38. 发明专利

JP2961530B2 Method of manufacturing a semiconductor flash memory device 失效
公开(公告)号：JP2961530B2
公开(公告)日：1999-10-12
申请号：JP5511798
申请日：1998-03-06
申请人：エルジーセミコンカンパニーリミテッド
发明人： HE CHEORU JEON
IPC分类号： H01L21/8247 , G11C11/34 , G11C11/38 , H01L21/28 , H01L27/10 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L29/42332 , H01L21/28273
摘要： A flash memory device and fabrication method simplify the fabrication process of a semiconductor EEPROM device through a self-aligning process. The device includes a semiconductor substrate in which source and drain regions are defined, a first insulation layer formed on the semiconductor substrate, a first conductive layer pattern formed on a portion of the first insulation layer, sidewall spacers formed of a second conductive layer neighboring each sidewall of the first conductive layer pattern and covered by second and third insulation layers, and a third conductive layer pattern formed on the insulation layers and connected with the first conductive layer pattern.

39. 发明专利

JPH10200001A MEMORY DEVICE 失效
公开(公告)号：JPH10200001A
公开(公告)日：1998-07-31
申请号：JP31330997
申请日：1997-11-14
申请人： HITACHI LTD
发明人： NAKAZATO KAZUO , ITO KIYOO , MIZUTA HIROSHI , SATO TOSHIHIKO , SHIMADA JUICHI , HARUN AHMED
IPC分类号： G11C11/38 , G11C14/00 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/66 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a memory device having a tunnel barrier structure with a reduced write, read and erase time. SOLUTION: The device has memory nodes 1 for writing charges passed through a multiple tunnel barrier structure 2. The stored charge gives influence on the conductivity of a source-drain path 4. The conductivity of this path 4 is monitored to read data. The charge barrier structure is a multiple tunnel barrier structure 2 which is composed of alternately laminated polysilicon layers 16 3nm thick and Si3 N4 layers 15 1nm thick 4, covering a polycrystal layer of Si which forms the memory nodes 1, or may be a barrier structure which includes a Schottky barrier structure and conductive nano-scale conductive islands dispersed in an electric insulation matrix, acting as memory nodes.

40. 发明专利

JPH1098160A UNPAIRED ELECTRON MEMORY CELL DEVICE 失效
公开(公告)号：JPH1098160A
公开(公告)日：1998-04-14
申请号：JP15308497
申请日：1997-05-28
申请人： SIEMENS AG
发明人： RISCH LOTHAR , ROESNER WOLFGANG
IPC分类号： G11C11/38 , G11C11/34 , G11C11/40 , G11C11/404 , H01L27/10 , H01L27/28 , H01L51/05
摘要： PROBLEM TO BE SOLVED: To easily drive memory cells with adequate voltage levels given to first and second attached leads by connecting the memory cells having unpaired electron memory elements and unpaired electron transistors between the first and second leads. SOLUTION: Memory cells each have six tunnel elements T1-T6, mutually connected vertically through tunnel contacts TK. The first tunnel element T1 is connected to a first lead L1 terminal through a first tunnel contact TY1. The row last tunnel element T6 is connected to a memory node SK through a second tunnel contact TK2. This node SK is capacitively drivable through a first gate electrode G1. The distance between the memory node SK and the first gate electrode G1 is sufficient to impede a memory cell device from the tunnel moving with a predetermined working voltage.

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