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1. 发明专利

JP2003133437A SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：JP2003133437A
公开(公告)日：2003-05-09
申请号：JP2001326757
申请日：2001-10-24
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KUJIRAI YUTAKA , SHIGENIWA MASAHIRO , NAKAZATO KAZUO , KISU TERUAKI , MATSUOKA HIDEYUKI , TABATA TAKESHI , HAGA SATORU
IPC分类号： H01L21/768 , H01L21/334 , H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/78 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To improve reliability of a semiconductor device having a vertical transistor for memory cell selection. SOLUTION: A vertical MIS Qvn is provided immediately on a grooved capacitor 6 provided to a semiconductor substrate 1S in a memory cell region, and a lateral nMIS Qn is provided to a semiconductor substrate in a peripheral circuit region. After the capacitor 6 is formed, a lateral nMIS Qn is formed. After a lateral nMIS Qn is formed, a vertical MIS Qvn is formed. Furthermore, after a capacitor is formed, a separation part 10 of a peripheral circuit region is formed.

2. 发明专利

JP2002203913A SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
公开(公告)号：JP2002203913A
公开(公告)日：2002-07-19
申请号：JP2000401596
申请日：2000-12-28
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KISU TERUAKI , NAKAZATO KAZUO , TAKAHASHI MASATO
IPC分类号： H01L21/8239 , H01L21/8242 , H01L27/06 , H01L27/105 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a gain cell structure which can reduce the size of a memory cell and to provide a method by which the structure can be manufactured inexpensively. SOLUTION: The memory cell is constituted of one read MIS transistor QR and one write MIS transistor QW. The transistor QR as a pair n+-type semiconductor areas (a source area and a drain area) 13 and 13 formed on the main surface of a substrate 1, and first gate electrodes 5a formed on the paths of the areas 13 and 13 through first gate insulating films 4. The write MIS transistor QW is arranged above the read MIS transistor QR and has a vertical structure in which a laminated structure formed by laminating a lower semiconductor layer 6a (source area), an intermediate semiconductor layer 6b (channel forming area, and an upper semiconductor layer 6c (drain area) upon another in this order and second gate electrode 19 are arranged, with the electrodes 19 being arranged on both side faces of the laminated structure through second gate insulating films 18.

3. 发明专利

JPH0560266B2 失效
公开(公告)号：JPH0560266B2
公开(公告)日：1993-09-01
申请号：JP1006584
申请日：1984-01-25
申请人： HITACHI LTD
发明人： NAKAZATO KAZUO , NAKAMURA TOORU , KATO MASATAKA , MYAZAKI TAKAO , OKABE TAKAHIRO
IPC分类号： H01L29/41 , H01L29/423 , H01L29/78 , H01L29/784

4. 发明专利

JPH0558263B2 失效
公开(公告)号：JPH0558263B2
公开(公告)日：1993-08-26
申请号：JP22204183
申请日：1983-11-28
申请人： HITACHI LTD
发明人： NAKAZATO KAZUO , NAKAMURA TOORU , KAWAMOTO YOSHIFUMI
IPC分类号： H01L27/04 , H01L21/28 , H01L21/302 , H01L21/822 , H01L29/40 , H01L29/43 , H01L29/46

5. 发明专利

JPH01123470A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH01123470A
公开(公告)日：1989-05-16
申请号：JP28103387
申请日：1987-11-09
申请人： HITACHI LTD
发明人： HORIUCHI KATSUTADA , NAKAZATO KAZUO
IPC分类号： H01L21/76 , H01L21/331 , H01L21/336 , H01L21/8234 , H01L27/06 , H01L27/08 , H01L27/088 , H01L29/08 , H01L29/72 , H01L29/73 , H01L29/732 , H01L29/78
摘要： PURPOSE:To form a buried insulating film in a self alignment manner with the side wall of a semiconductor substrate, and realize miniaturization, by a method wherein, after protrusion type semiconductor regions are formed by forming a trench in the vertical direction in a substrate, a horizontal hole is formed in the bottom part of the trench, and an insulating film is buried in said horizontal hole. CONSTITUTION:After a buried layer 2 is formed in a substrate 1, an epitaxial layer 3 is formed on the surface, and successively, an SiO2 film 30, an Si3N4 film 21 and an SiO2 film 22 are formed in order. By forming a trench H1 in the films 20-22 and the epitaxial layer 3, protrusion type semiconductor regions A, B are formed. After an oxidization resistant coating film 23 is formed on the side wall part of the protrusion type semiconductor regions A, B, the above trench H is etched more deeply. By anisotropic etching in the direction of 110 axis, a trench H2 is formed in the side wall bottom part of the above protrusion type regions A, B. The substrate surface of the bottom of the trench is composed of 111 face. After a buried insulating film 6 is formed in the trench, lead-out electrodes 7, 13 are formed on the insulating film 6.

6. 发明专利

JPS63142673A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63142673A
公开(公告)日：1988-06-15
申请号：JP28879386
申请日：1986-12-05
申请人： HITACHI LTD
发明人： WASHIO KATSUYOSHI , NAKAMURA TORU , NAKAZATO KAZUO
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72 , H01L29/732
摘要： PURPOSE:To form a transistor and an integrated circuit which are operated at a high speed and whose integration density is high by a method wherein the impurity concentration of a third region is higher than that of a fourth region and a junction position for the third region and a second region is situated at a part which is nearer to the surface than the junction position of the fourth region and the second region. CONSTITUTION:An insulating film 77 is formed at the side part of a protrusion-type monocrystalline semiconductor layer 3; a polycrystalline semiconductor layer 6 is connected to the corner part near the surface of the recessed-type single-crystalline semiconductor layer 3 in such a way that the width at the connected part is definite to be less than 0.1mum; the polycrystalline semiconductor layer near the connecting part is made thin. With this structure, the diffusion from the polycrystalline semiconductor layer 6 preliminarily doped with an impurity can be suppressed, and the distance of a P type region 14 from an n type buried layer 2 is made longer than that from a p type region 4. Accordingly, the space between a third high-concentration region, of a first conductivity type, connected to a second single-crystalline or polycrystalline semiconductor layer and a buried layer, of a second conductivity type, can be made wider than the space between a fourth low-concentration region, of the first conductivity type, and a first region; as a result, it is possible to reduce the capacitance between a base and a collector for a bipolar transistor and to realize a high-speed transistor.

7. 发明专利

JPS6364356A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6364356A
公开(公告)日：1988-03-22
申请号：JP20785086
申请日：1986-09-05
申请人： HITACHI LTD
发明人： ISHIKAWA MICHIO , WASHIO KATSUYOSHI , NAKAZATO KAZUO , NAKAMURA TORU
IPC分类号： H01L27/04 , H01L21/331 , H01L21/822 , H01L29/72 , H01L29/73 , H01L29/732
摘要： PURPOSE:To improve the degree of integration and high-frequency characteristics by sharing a leading-out electrode in conductivity type polycrystalline Si as one electrode for a capacitor and a base electrode for a side-wall base electrode structure transistor. CONSTITUTION:A thermal oxide film 2 is formed onto a semiconductor substrate 1, a transistor region 11 as a projecting section is shaped, and a polycrystalline Si layer 3 is formed. An unnecessary section in the Si layer 3 is changed into a thermal oxide film 4, and an impurity is introduced to the Si layer 3. A thermal oxide film 6 is shaped through thermal oxidation while P-type diffusion layers 12 are formed on the side walls of the region 11. The oxide film 6 only in a capacitor section is removed, an Si nitride film 7 is grown, and polycrystalline Si layers 8 are grown. An impurity is introduced to the Si layers 8, and the layers 8 are etched. As a final step, an Al electrode 9 sharing one electrode for the capacitor and a base electrode for a transistor and the other electrode 10 for the capacitor are formed to contact holes.

8. 发明专利

JPS636876A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS636876A
公开(公告)日：1988-01-12
申请号：JP14950586
申请日：1986-06-27
申请人： HITACHI LTD
发明人： USAGAWA TOSHIYUKI , NAKAZATO KAZUO , UMEMOTO YASUNARI , HIRUMA TAKEYUKI
IPC分类号： H01L29/872 , H01L21/331 , H01L27/06 , H01L27/10 , H01L29/205 , H01L29/47 , H01L29/72 , H01L29/73 , H01L29/737
摘要： PURPOSE:To prevent a soft error from being produced by alpha rays by forming an emitter layer on the side of a substrate and a collector layer on a surface. CONSTITUTION:After an undoped AlGaAs layer 11 and undoped GaAs are formed on a semi-insulative GaAs substrate, Si ions are implanted in regions 15 and 16 to be an emitter. Then, ramp annealing is performed to activate Si atoms. Then, an uppermost GaAs layer used as a protective film for the layer 11 is thermally decomposed in an MBE chamber. Then, a p-type GaAs layer 12 containing Be is formed and an n collector layer 13 containing Si and then an n-type GaAs collector layer 14 containing Si are formed. Thus, since the inflow of hole and electron pairs due to alpha particles flowing into the collector layer can be prevented, the alpha ray soft error of an SRAM can be reduced by four figures as compared with the conventional.

9. 发明专利

JPS62195173A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62195173A
公开(公告)日：1987-08-27
申请号：JP3524186
申请日：1986-02-21
申请人： HITACHI LTD
发明人： SHIBA TAKEO , NANBA MITSUO , NAKAMURA TORU , NAKAZATO KAZUO
IPC分类号： H01L29/73 , H01L21/331 , H01L29/72 , H01L29/732
摘要： PURPOSE:To reduce the ratio of the transit time of carriers in graft base regions to the total transit time of carriers in an SICOS type bipolar transistor by a method wherein inclinations spreading toward the depth direction are provided on the side walls of a single crystal semiconductor layer which is contacted with nonactive base regions. CONSTITUTION:After an n type buried layer 4 is formed in a p-type Si substrate, 1 an n-type Si epitaxial layer 3 and, selectively, Si oxide films 5 are formed. The layer 3 is etched with the oxide films 5 as masks to form isolation trenches 2. At that time, inclinations spreading toward the depth direction are provided on the side walls 30 of the layer 3. After Si oxide films 8 are formed on the parts of the side walls 30 of the layer 3 and Si oxide films 6 are formed in the isolation trenches 2, a polycrystalline Si layer 7 is deposited over the whole surface. After the layer 7 is doped with a p-type impurity, the layer 7 is removed by etching except nonactive base regions 9. After that a hot oxide film 10 is formed. Then a p-type impurity is diffused into the layer 3 by hot diffusion to form graft base regions 11. Then a p-type active base region 12, an n-type emitter region 14, an n-type collector region 13 and electrodes 15 are formed.

10. 发明专利

JPS61253855A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61253855A
公开(公告)日：1986-11-11
申请号：JP9543085
申请日：1985-05-07
申请人： HITACHI LTD
发明人： KIMURA SHINICHIRO , OKURA OSAMU , NAKAGAWA KIYOKAZU , ISHIZAKA AKITOSHI , SHIRAKI YASUHIRO , SUGASHIRO SHIYOUJIROU , WADA YASUO , NAKAZATO KAZUO , SHIMOHIGASHI KATSUHIRO
IPC分类号： H01L21/8238 , H01L21/20 , H01L27/06 , H01L27/092 , H01L29/45 , H01L29/78
摘要： PURPOSE:To obtain a two-layer-type CMOS structure optimal for micrifying elements, by providing an intermediate layer of a metal or a silicide thereof between a source and a drain where ohmic contact is required. CONSTITUTION:A silicon substrate 4.1 is provided thereon with a thick insulation film 4.2 for isolating elements, a gate oxide film 4.3, a gate electrode 4.4, a source 4.5 and a drain 4.6 so that a MOSFET is formed. An insulation film 4.7 is deposited thereon and is provided with contact holes in the source and the drain. A single-crystal metal or a silicide thereof is epitaxially grown on the source region 4.5 in the aperture of the contact hole. When the vapor deposi tion is performed under a ultra-high vacuum, the metal is deposited in the single crystal state on the exposed portion of the single-crystal substrate while it is deposited in the polycrystalline state on the insulation film 4.7. Etching is then performed so as to leave the single crystal metal or the silicide thereof on the source region 4.5 only. According to this method, the dimensions of the element can be substantially decreased in comparison with a conventional two-layer-type CMOS which requires contact holes to be provided separately.

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