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31. 发明专利

JP2008177316A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008177316A
公开(公告)日：2008-07-31
申请号：JP2007008720
申请日：2007-01-18
申请人： Toshiba Corp , 株式会社東芝
发明人： GOTO MASAKAZU , KAWANAKA SHIGERU
IPC分类号： H01L29/78 , H01L21/28 , H01L29/41 , H01L29/423 , H01L29/49
CPC分类号： H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/28105 , H01L29/42376 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that suppresses a drop in On-state current of a transistor while having a gate electrode that prevents the occurrence of depletion effects and suppresses oxidation in a manufacturing process, corrosion due to chemicals, and contamination of a heat treatment device due to metals contained in the gate electrode, and its manufacturing method.
SOLUTION: The semiconductor device has a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a metal-containing layer formed on the gate insulating film, and a gate electrode comprising a polycrystalline silicon layer that includes impurity ions covering the upper face and side faces of the metal-containing layer.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决方案：提供一种半导体器件，其抑制晶体管的导通电流的下降，同时具有防止耗尽效应的发生并抑制制造过程中的氧化的栅电极，由于化学品引起的腐蚀，以及由于栅电极中含有的金属而引起的热处理装置的污染及其制造方法。解决方案：半导体器件具有半导体衬底，形成在半导体衬底上的栅极绝缘膜，形成在栅极绝缘膜上的含金属层，以及包括多晶硅层的栅电极，该多晶硅层包括覆盖含金属层的上面和侧面。版权所有（C）2008，JPO＆INPIT

32. 发明专利

JP2003124463A SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003124463A
公开(公告)日：2003-04-25
申请号：JP2002235089
申请日：2002-08-12
申请人： TOSHIBA CORP
发明人： USHIKU YUKIHIRO , MIZUNO TOMOHISA , YOSHIMI MAKOTO , TERAUCHI MAMORU , KAWANAKA SHIGERU
IPC分类号： H01L29/786 , H01L21/336 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can improve element characteristics. SOLUTION: The semiconductor device is provided with a substrate 21 having a projecting semiconductor element region 23 and a gate electrode 26 which is formed on the upper and lateral side of the element region 23 with gate insulating films 25a and 25b interlaid. In the element region 23, a source region and a drain region are provided separately from each other so that a channel region is formed opposite to the gate electrode 26. At least one selected from the group consisting of the film thickness of the gate insulating films 25a and 25b, the material of the gate insulating films and the material of the gate electrode is different between the upper side of the element region 23 and the lateral side thereof.

33. 发明专利

JP2003069035A Semiconductor device and semiconductor integrated circuit 有权
标题翻译：半导体器件和半导体集成电路
公开(公告)号：JP2003069035A
公开(公告)日：2003-03-07
申请号：JP2002167156
申请日：2002-06-07
申请人： Toshiba Corp , 株式会社東芝
发明人： KAWANAKA SHIGERU
IPC分类号： H01L27/04 , H01L21/822 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device where the operating speed is high and at the same time power consumption is small even if an SOI element is used, and to provide a semiconductor integrated circuit.
SOLUTION: The semiconductor device is equipped with a semiconductor layer that is provided on a semiconductor substrate via an insulation film. On the semiconductor layer, a gate electrode is provided via a gate insulation film, and a pair of source/drain regions is formed in the semiconductor layer so that a body region under the gate electrode is sandwiched. A control section supplies voltage between the source/drain regions. The control section supplies a first voltage and a second voltage that differs from the first one between the source/drain regions while the semiconductor device is off and on, and the second voltage is set so that potential in a body region in an off state becomes substantially the same as that in the body region in an on state.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：为了提供一种半导体器件，其中，即使使用SOI元件，工作速度高，同时功耗小，并且提供半导体集成电路。解决方案：半导体器件配备有通过绝缘膜设置在半导体衬底上的半导体层。在半导体层上，通过栅极绝缘膜设置栅电极，并且在半导体层中形成一对源极/漏极区，使得栅电极下方的体区被夹持。控制部分在源极/漏极区域之间提供电压。控制部分在半导体器件断开和接通时提供与源极/漏极区域之间的第一电压和第二电压不同的第一电压和第二电压，并且第二电压被设置为使得处于关闭状态的体区域中的电位变为基本上与处于开状态的身体区域中相同。

34. 发明专利

JPH11330089A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH11330089A
公开(公告)日：1999-11-30
申请号：JP18784698
申请日：1998-07-02
申请人： TOSHIBA CORP
发明人： SHINO TOMOAKI , KAWANAKA SHIGERU , TERAUCHI MAMORU , YAMADA TAKASHI , YOSHIMI MAKOTO , YOSHITOMI SADAYUKI , INO KAZUMI , ARAI HIDEAKI
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8234 , H01L27/06
摘要： PROBLEM TO BE SOLVED: To reduce parasitic resistance of a base of a lateral bipolar transistor, emitter-to-base parasitic junction capacity and restrain characteristic dispersion caused by a length of a base lead-out region, a length of an emitter/base junction part, and fluctuations of a relative formation position of an emitter and a collector. SOLUTION: Two mask patterns which are almost at right angles to each other are used and an emitter region 11, base regions 13, 16, a base lead-out region 18, etc., of a lateral bipolar transistor can be formed to self-aligned to a side surface of each mask. Since each region is formed to self-align to two mask patterns in this way, position relation of each region can be controlled accurately, without the dependence on mask alignment precision. As a result, a bipolar transistor of small parasitic capacity and parasitic resistance can be manufactured with high reproducibility.

35. 发明专利

JPH1197693A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH1197693A
公开(公告)日：1999-04-09
申请号：JP25507297
申请日：1997-09-19
申请人： TOSHIBA CORP
发明人： KAWANAKA SHIGERU
IPC分类号： H01L21/336 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To effectively eliminate such adverse effects on SOI(silicon on insulator) elements as parasitic capacitances induced by providing contacts at source and drain regions and body regions which are held between embedded oxide films for these regions, and increase in the leakage current. SOLUTION: For forming a contact for giving a potential to a channel region of an SOI element with a body current, in a parasitic MOS capacitor region less contributing the element current drive force, its inverted threshold voltage is controlled to reduce the parasitic capacitance at this region and leak current, etc., within an actual operating voltage range. An impurity is added to the desired region or the work function of a gate electrode 3-8 at a parasitic MOS region 3-5 formed near a body contact region 3-9 of the SOI element with the body current is changed, so that the inverted threshold voltage of this MOS region can be set independently of that of the SOI element.

36. 发明专利

JPH10256556A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH10256556A
公开(公告)日：1998-09-25
申请号：JP6120297
申请日：1997-03-14
申请人： TOSHIBA CORP
发明人： YAMADA TAKASHI , KAWANAKA SHIGERU , WATANABE SHIGEYOSHI , MATSUZAWA KAZUYA , OWAKI YUKITO
IPC分类号： H01L21/336 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To make elements fine, without increasing the wiring resistance of a body in a channel direction by providing a body region having a larger film thickness than that of at least one of the source and drain and a predetermined potential given from a contact. SOLUTION: On a substrate 1 an insulation film 2 and semiconductor layer 3 are formed. This layer 3 has a laminate structure of a high resistance 3-1 and low resistance 3-2 to reduce the delay of the body. On this layer 3 source and drain diffused layers 6-1, 6-2 are formed with a body region 7 between them. This region has a larger film thickness than that of at least one of the source and drain diffused layers 6-1, 6-2 and specified potential is given to it from a contact 9-2 to thereby make elements fine, without increasing the wiring resistance in the channel direction of the body.

37. 发明专利

JP2012146817A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012146817A
公开(公告)日：2012-08-02
申请号：JP2011003907
申请日：2011-01-12
申请人： Toshiba Corp , 株式会社東芝
发明人： MIYATA TOSHINORI , KAWANAKA SHIGERU , ADACHI KANNA
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/772 , H01L29/0895 , H01L29/1054 , H01L29/1608 , H01L29/165 , H01L29/6656 , H01L29/7836
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of improving MOSFET characteristics and to provide a method of manufacturing the same.SOLUTION: A semiconductor device according to the present invention comprises: a substrate; a gate electrode formed above the substrate; a gate insulating film formed under the gate electrode; a channel layer formed by a channel-layer material having a wider band gap than a material of the substrate, under the gate insulating film; a source region and a drain region formed in the substrate along the channel direction so as to sandwich the channel layer; and a source extension layer that is formed in the substrate between the channel layer and the source region so as to overlap the side end portion of the channel layer at the source side, and that forms with the channel layer a heterointerface in which carriers tunnel.
摘要翻译：要解决的问题：提供能够改善MOSFET特性并提供其制造方法的半导体器件。解决方案：根据本发明的半导体器件包括：衬底; 形成在所述衬底上的栅电极; 形成在栅电极下方的栅极绝缘膜; 由栅极绝缘膜下方的沟道层材料形成的沟道层材料具有比衬底材料更宽的带隙; 源极区域和漏极区域，沿着沟道方向形成在衬底中，以夹持沟道层; 以及源极延伸层，其形成在沟道层和源极区域之间的衬底中，以与源极侧的沟道层的侧端部重叠，并且与沟道层形成载流子隧道的异质界面。版权所有（C）2012，JPO＆INPIT

38. 发明专利

JP2012084797A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2012084797A
公开(公告)日：2012-04-26
申请号：JP2010231634
申请日：2010-10-14
申请人： Toshiba Corp , 株式会社東芝
发明人： ADACHI KANNA , KAWANAKA SHIGERU , INABA SATOSHI
IPC分类号： H01L27/10 , H01L21/768
CPC分类号： H01L27/1104 , H01L27/11 , H01L29/4238
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having an SRAM cell with low power consumption using transistors having small variation in characteristics.SOLUTION: A semiconductor device includes an SRAM cell formed on a semiconductor substrate. N-type source regions of a first and second load transistors, n-type drain regions of a first and second driver transistors, and n-type source regions and n-type drain regions of a first and second transfer transistors are located in regions other than the region between any of two regions in p-type drain regions of the first and second load transistors and p-type source regions of the first and second driver transistors.
摘要翻译：解决的问题：使用具有小的特性变化的晶体管来提供具有低功耗的SRAM单元的半导体器件。解决方案：半导体器件包括形成在半导体衬底上的SRAM单元。第一和第二负载晶体管的N型源极区域，第一和第二驱动晶体管的n型漏极区域，以及第一和第二转移晶体管的n型源极区域和n型漏极区域位于其他区域比第一和第二负载晶体管的p型漏极区域中的两个区域中的任一个区域以及第一和第二驱动器晶体管的p型源极区域之间的区域。版权所有（C）2012，JPO＆INPIT

39. 发明专利

JP2011243716A Spin transistor and integrated circuit 审中-公开
标题翻译：旋转晶体管和集成电路
公开(公告)号：JP2011243716A
公开(公告)日：2011-12-01
申请号：JP2010113873
申请日：2010-05-18
申请人： Toshiba Corp , 株式会社東芝
发明人： KAWANAKA SHIGERU , ADACHI KANNA , KONDO YOSHIYUKI
IPC分类号： H01L29/82 , H03K19/18
CPC分类号： H01L29/66984 , G11C11/16 , H01F10/1936
摘要： PROBLEM TO BE SOLVED: To provide a spin transistor and an integrated circuit where power consumption is suppressed and an increase of an occupied area is suppressed.SOLUTION: A spin transistor according to an embodiment includes: a first magnetic material region that has a first input terminal and is polarized in a first magnetization direction by a first signal inputted through the first input terminal; a second magnetic material region that has a second input terminal and is polarized in a second magnetization direction opposite to the first magnetization direction by a second signal that is inputted through the second input terminal and is different from the first signal; and a third magnetic material region that has a third input terminal and a first output terminal, is polarized in the first magnetization direction by a third signal inputted through the third input terminal to output, through the first output terminal, the first signal supplied from the first magnetic material region, and is polarized in the second magnetization direction by a fourth signal inputted through the third input terminal and different from the third signal to output, through the first output terminal, the second signal supplied from the second magnetic material region.
摘要翻译：要解决的问题：提供抑制功耗并且抑制占用面积的增加的自旋晶体管和集成电路。解决方案：根据实施例的自旋晶体管包括：第一磁性材料区域，其具有第一输入端子，并且通过通过第一输入端子输入的第一信号在第一磁化方向上被极化; 第二磁性材料区域，具有第二输入端子，并且通过第二输入端子输入并与第一信号不同的第二信号在与第一磁化方向相反的第二磁化方向上被极化; 并且具有第三输入端和第一输出端的第三磁性材料区域在第一磁化方向上被通过第三输入端子输入的第三信号极化，以通过第一输出端子输出从第一磁性材料区域，并且通过第三输入端子输入的与第三信号不同的第四信号沿第二磁化方向极化，以通过第一输出端子输出从第二磁性材料区域提供的第二信号。版权所有（C）2012，JPO＆INPIT

40. 发明专利

JP2011192667A Transistor and method of manufacturing the same 审中-公开
标题翻译：晶体管及其制造方法
公开(公告)号：JP2011192667A
公开(公告)日：2011-09-29
申请号：JP2010054853
申请日：2010-03-11
申请人： Toshiba Corp , 株式会社東芝
发明人： MIYATA TOSHITAKA , NAKABARAI SHU , KAWANAKA SHIGERU , ADACHI KANNA
IPC分类号： H01L29/66 , H01L21/28 , H01L29/06 , H01L29/786 , H01L51/05 , H01L51/30 , H01L51/40
CPC分类号： H01L29/1606 , B82Y10/00 , B82Y30/00 , H01L29/0895 , H01L29/7391 , H01L29/7781 , H01L29/7839 , H01L29/78684 , H01L29/78696 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To provide a transistor that has high current driving force and high cutoff characteristics, and to provide a method of manufacturing the same. SOLUTION: The transistor 100 in one embodiment includes: a graphene film 10 which has a conductor region 10a and a semiconductor region 10b where atoms are bonded to a surface, and functions as a channel; and a gate electrode 12 formed on the graphene film 10 with a gate insulating film 11 interposed, wherein a tunnel current of a Schottky junction that is formed by the conductor region 10a and semiconductor region 10b is used for switching operation. COPYRIGHT: (C)2011,JPO&INPIT

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