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31. 发明专利

JPS6151700A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：JPS6151700A
公开(公告)日：1986-03-14
申请号：JP17332884
申请日：1984-08-22
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： KAJITANI KAZUHIKO , MIYAZAWA KAZUYUKI , MURANAKA MASAYA , II HARUO , KAJIMOTO TAKESHI
IPC分类号： G11C29/00 , G11C29/34 , G11C29/44
摘要： PURPOSE: To improve the detection rate of inferior goods by driving an output buffer based on an coincidence detection output under a test operation, and shortening the quality test time, without increasing chip size.
CONSTITUTION: When a test control signal ϕt is applied, gates of ANA circuits G
4 and G
5 on a logic gate portion LG are closed and gates of G
3 and G
6 are opened. A reading data passing through main amplifiers MA
1 WMA
4 are not supplied to NOR circuits G
7 , G
8 and outputs of NAND circuits G
1 and G
2 connected to common input and output wires I/O
1 WI/O
4 are supplied to G
7 and G
8 . When only one of the data read out from the same address position of memory mats 1aW1d is different, the outputs of G
1 and G
2 are considered to be high level and G
7 and G
8 are to be low level, G
1 and G
2 constituting an output buffer DOB are turned off, an error writing is detected and the inferior goods can be decided.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过在测试操作下基于一致检测输出驱动输出缓冲器，提高劣质检测率，缩短质量检测时间，不增加芯片尺寸。构成：当施加测试控制信号phit时，逻辑门部分LG上的ANA电路G4和G5的栅极闭合，并且G3和G6的栅极被打开。通过主放大器MA1-MA4的读取数据不被提供给NOR电路G7，G8，并且连接到公共输入和输出线I / O1-I / O4的NAND电路G1和G2的输出被提供给G7和G8。当从存储器垫1a-1d的相同地址位置读出的数据中只有一个不同时，G1和G2的输出被认为是高电平，G7和G8为低电平，G1和G2构成输出缓冲区DOB被关闭，检测到错误写入，并且可以确定劣质商品。

32. 发明专利

JPS6122493A Decoder circuit 失效
标题翻译：解码器电路
公开(公告)号：JPS6122493A
公开(公告)日：1986-01-31
申请号：JP14237984
申请日：1984-07-11
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： MURANAKA MASAYA , KAJIMOTO TAKESHI , MATSUURA NOBUMI
IPC分类号： G11C11/408 , G11C11/34
摘要： PURPOSE: To offset leak current without increasing an occupied area, to secure a decoder output at non-selection for a long period and to prevent the multiple selection by connection a high resistance element in parallel to a precharge MOSFET and compensating the leak current.
CONSTITUTION: A node x
0 is made at H level by a precharged pulse ϕp through a P-channel FETQp. As long as any one of address input N-channel FETs Q
21 , Q
22 ... is off in the nonselective state through a row address buffer X-ADB, the node x
0 is brought into the H level nonselective state. In such a case, the leak current can be compensated by the P-channel FETQr of a high resistance element, which is always on in parallel with the FETQp, through the FETs Q
21 , Q
22 .... Thus the leak current can be canceled out without increasing an occupied area, and a decoder output at the non-selection can be secured for a long time, thereby preventing the occurrence of erroneous operation at multiple selection.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：为了在不增加占用面积的情况下消除泄漏电流，长时间保证解码器输出处于非选择状态，并通过连接高电阻元件并与预充电MOSFET并补偿漏电流来防止多重选择。构成：通过P沟道FETQp通过预充电脉冲激光器在H电平上使节点x0成为。只要地址输入N沟道FET Q21，Q22 ...中的任何一个在非选择状态下通过行地址缓冲器X-ADB截止，则节点x0进入H电平非选择状态。在这种情况下，可以通过FET Q21，Q22 ...总是与FETQp并联的高电阻元件的P沟道FETQr来补偿漏电流。因此，漏电流可以被取消在不增加占用面积的情况下，可以长时间确保非选择时的解码器输出，从而防止多次选择时发生错误操作。

33. 发明专利

JP2002133876A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JP2002133876A
公开(公告)日：2002-05-10
申请号：JP2000323043
申请日：2000-10-23
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： MURANAKA MASAYA , ITO YUTAKA
IPC分类号： G11C11/401 , G11C11/405 , G11C11/56 , G11C16/04 , H01L21/8242 , H01L27/105 , H01L27/108 , H01L27/115 , H01L27/12
摘要： PROBLEM TO BE SOLVED: To provide a highly reliable and user-friendly semiconductor memory which realizes high large storage capacity. SOLUTION: A memory cell comprising a MOSFET holding information voltage of ternary or more in its gate, a transistor for write-in giving information voltage of ternary or more to a gate of the MOSFET, and a transistor for read-out connected in series to the MOSFET are used, plural reference voltages corresponding to the information voltage of ternary or more are applied to a source of the MOSFET by a source line, digital data is formed by combination of on-state/off-state of the MOSFET corresponding to plural reference voltages, or source voltage of the MOSFET is outputted as it is as read-out voltage.

34. 发明专利

JP2002074995A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JP2002074995A
公开(公告)日：2002-03-15
申请号：JP2000258315
申请日：2000-08-29
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： FUKUOKA KANTATSU , KATO HIDEAKI , MURANAKA MASAYA
IPC分类号： G01R31/28 , G01R31/3185 , G11C11/401 , G11C11/407 , G11C11/413 , G11C16/06 , G11C17/00 , G11C29/00 , G11C29/14
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory in which a short circuit between bit lines having a comparatively high resistance can be screened easily. SOLUTION: In the semiconductor memory constituted so that an input/output terminal of a memory cell connected to a word line is made conductive with a corresponding bit line by that the word line is driven to a selection level, while a potential appearing on a bit line by input/output of a data signal is amplified by a sense amplifier, the memory has a normal operation mode in which amplifying operation by the sense amplifier is started simultaneously with timing at which the word line is driven to a selection level and amplifying operation by the sense amplifier is finished simultaneously with timing at which a level of the word line is reduced from a selection level to a non-selection level or after that, and a test mode in which start of amplifying operation by the sense amplifier is performed later by the prescribed period than that in the normal operation mode or finish of amplifying operation by the sense amplifier is performed before timing at which a level of the word line is reduced to a non-selection level by quickening it more by the prescribed period than that in the normal operation mode.

35. 发明专利

JPH06275693A DYNAMIC RAM 失效
公开(公告)号：JPH06275693A
公开(公告)日：1994-09-30
申请号：JP8557693
申请日：1993-03-20
申请人： HITACHI LTD , TEXAS INSTRUMENTS JAPAN
发明人： MATSUURA NOBUMI , MURANAKA MASAYA , ORITO YASUNORI
IPC分类号： G01R31/28 , G11C11/401 , G11C29/00 , G11C29/18 , G11C29/34 , H01L21/66
摘要： PURPOSE:To provide a dynamic RAM having a testing circuit which can variously test an internal circuit. CONSTITUTION:A memory array is logically or physically divided into a plurality of blocks to be tested at a block unit. A memory array having a plurality of column address strobe signals to be accessed at a unit of a plurality of bits corresponding to the signals can test independently of the corresponding array by using the signals. Accordingly, since the test can be conducted in terms of a plurality of memory arrays which are logically or physically divided, a precise evaluation, a malfunction analysis can be executed with less samples.

36. 发明专利

JPH04362592A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH04362592A
公开(公告)日：1992-12-15
申请号：JP16350991
申请日：1991-06-08
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUZUKI YUKIE , MURANAKA MASAYA , MATSUURA NOBUMI , NAKAGOME YOSHINOBU , TANAKA HITOSHI , YAMAZAKI EIJI , SAKUTA TOSHIYUKI
IPC分类号： G11C11/401 , G11C7/10 , G11C11/409 , G11C29/00 , G11C29/34 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To expand the number of parallel bits in the multi-bit parallel test mode of a dynamic RAM, etc., without being restricted with the number of sub IO line. CONSTITUTION:A memory array is constituted of memory mats from MAT00 L-MAT07L to MAT10R-MAT17R, etc., and a first common data line where a bit line is connected selectively, that is, the sub IO line and a second common data line where the sub IO line is connected selectively, that is, main IO lines group MI0G0-MI0G7 are provided. A main amplifier constituting a main amplifier unit MAU0 and arranged to align in the direction of the prolongation of a word line is provided with a first main amplifier necessitating relatively large operating current and second main amplifier necessitating relatively small operating current, and the main amplifier is chosen according to an operating mode.

37. 发明专利

JPH04181591A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH04181591A
公开(公告)日：1992-06-29
申请号：JP30891590
申请日：1990-11-16
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUZUKI YUKIE , MURANAKA MASAYA , MATSUURA NOBUMI
IPC分类号： G11C11/407 , G11C11/401
摘要： PURPOSE:To enable memory capacity to be increased and these to be laid out easily by extending and placing an address decoder for forming word line selection signal and a word line drive circuit in a parallel direction of each bit line. CONSTITUTION:A word driver 2 and a row address decoder 3 are extended and placed by directing them in a parallel direction of each complimentary bit lines DL0, DO0* (* indicates inversion or row enable) - DLn, DLn* and a unit circuit of the decoder 3 and the driver 2 can be placed matching pitch of a complimentary pitch line where the pitch is larger than that of word lines WL1 - WLm, thus enabling the driver 2 and the decoder 3 to be placed easily even if the wiring pitch is small accompanied by increase in memory capacity and miniaturization of circuit element.

38. 发明专利

JPH04155862A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH04155862A
公开(公告)日：1992-05-28
申请号：JP28148590
申请日：1990-10-18
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MURANAKA MASAYA , II HARUO , SUZUKI YUKIE , MATSUURA NOBUMI , YOSHIKAWA KAZUE , ABE JUNICHI , KOYAMA YOSHIHISA , ARAI KOJI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/10 , H01L27/108
摘要： PURPOSE:To enhance a semiconductor integrated circuit device provided with a complementary MISFET in electrostatic breakdown strength when a high voltage is applied to a well region by a method wherein a third semiconductor region which is of the same conductivity type with a first well region or a first semiconductor region and higher than the first well region in impurity concentration is provided to the primary surface of a semiconductor substrate. CONSTITUTION:An N-type well region 2 and a P-type well region 3 are provided onto the different regions of the primary surface of a P -type semiconductor substrate 1 respectively. The P -type semiconductor substrate 1 is set as low in impurity concentration as 1X10 [atoms/cm ] or so. The N-type well region 2 is made to serve primarily as a region where a P channel MISFET Qp of a complementary MISFET is arranged and set as intermediate in impurity concentration as 2X10 [atoms/cm ] or so. The P-type well region 3 is made to serve as a region where a N channel MISFET Qn of the complementary MISFET is arranged and set as intermediate in impurity concentration as 5X10 [atoms/cm ] or so higher than that of the P -type semiconductor substrate 1.

39. 发明专利

JPH0373488A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH0373488A
公开(公告)日：1991-03-28
申请号：JP20781089
申请日：1989-08-14
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： MURANAKA MASAYA
IPC分类号： G11C11/401 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To simplify subcolumn decoder circuits and to reduced a chip size in the data line direction by adding a precolumn selection line. CONSTITUTION:The precolumn selection line (PYS) allocated to plural column selection lines on memory mats M1 to M8 in common is extended to all the memory mats M1 to M8 in common. A selection signal transmitted by the PYS and predeciding output signals formed correspondingly to respective memory mats M1 to M8 are supplied to subdecoder circuits SCD1 to SCD4 to form one column selection signal. Consequently, the subcolumn decoder circuits SCD1 to SCD4 can be simplified and the chip size in the data line direction can be reduced.

40. 发明专利

JPH02246147A OUTPUT BUFFER AND PROTECTIVE CIRCUIT; SEMICONDUCTOR STORAGE DEVICE CONTAINING THEM; ITS TYPE DEVELOPMENT, LAYOUT SYSTEM AND TEST SYSTEM 失效
公开(公告)号：JPH02246147A
公开(公告)日：1990-10-01
申请号：JP6583889
申请日：1989-03-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TAKAHASHI YASUSHI , IWAI HIDETOSHI , OGUCHI SATOSHI , NAKAMURA TAKASHI , UCHIYAMA HIROYUKI , TAKEKUMA SHUNJI , SAKOMURA SHIGETOSHI , MIYAZAWA KAZUYUKI , ISHIHARA MASAMICHI , HORI RYOICHI , KIZAKI TAKESHI , KOYAMA YOSHIHISA , II HARUO , MURANAKA MASAYA , AOYANAGI HIDETOMO , MATSUURA NOBUMI
IPC分类号： G11C11/41 , G11C11/34 , G11C11/401 , G11C11/403 , G11C11/406 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/12 , H01L21/60 , H01L21/66 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L23/50 , H01L27/04 , H01L27/10 , H01L27/108
摘要： PURPOSE:To efficiently develop types of a semiconductor storage device by a method wherein a common semiconductor substrate provided with the following is prepared and is owned jointly by a plurality of package specifications: a plurality of bonding pads arranged in optimum positions according to individual package shapes; a bonding pad, for control, which makes selectively effective a plurality of buffers corresponding to the pads and the plurality of bonding pads. CONSTITUTION:On a common semiconductor substrate of a dynamic RAM, names of pads used in the dynamic RAM according to DIP and SOJ package specifications are mentioned at the inside of a dotted line; names of pads used in the dynamic RAM according to ZIP package specifications are mentioned at its outside. This dynamic RAM is classified into a total of 21 product types according to its bit constitution, its operating mode and its package shape. Accordingly, when a semiconductor substrate which is common to all of the 21 product types is prepared and one part of its photomask is changed or a bonding treatment is executed selectively on a prescribed pad, either of the product types can be realized in a alternative way.

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