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1. 发明专利

JPS6151700A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：JPS6151700A
公开(公告)日：1986-03-14
申请号：JP17332884
申请日：1984-08-22
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： KAJITANI KAZUHIKO , MIYAZAWA KAZUYUKI , MURANAKA MASAYA , II HARUO , KAJIMOTO TAKESHI
IPC分类号： G11C29/00 , G11C29/34 , G11C29/44
摘要： PURPOSE: To improve the detection rate of inferior goods by driving an output buffer based on an coincidence detection output under a test operation, and shortening the quality test time, without increasing chip size.
CONSTITUTION: When a test control signal ϕt is applied, gates of ANA circuits G
4 and G
5 on a logic gate portion LG are closed and gates of G
3 and G
6 are opened. A reading data passing through main amplifiers MA
1 WMA
4 are not supplied to NOR circuits G
7 , G
8 and outputs of NAND circuits G
1 and G
2 connected to common input and output wires I/O
1 WI/O
4 are supplied to G
7 and G
8 . When only one of the data read out from the same address position of memory mats 1aW1d is different, the outputs of G
1 and G
2 are considered to be high level and G
7 and G
8 are to be low level, G
1 and G
2 constituting an output buffer DOB are turned off, an error writing is detected and the inferior goods can be decided.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过在测试操作下基于一致检测输出驱动输出缓冲器，提高劣质检测率，缩短质量检测时间，不增加芯片尺寸。构成：当施加测试控制信号phit时，逻辑门部分LG上的ANA电路G4和G5的栅极闭合，并且G3和G6的栅极被打开。通过主放大器MA1-MA4的读取数据不被提供给NOR电路G7，G8，并且连接到公共输入和输出线I / O1-I / O4的NAND电路G1和G2的输出被提供给G7和G8。当从存储器垫1a-1d的相同地址位置读出的数据中只有一个不同时，G1和G2的输出被认为是高电平，G7和G8为低电平，G1和G2构成输出缓冲区DOB被关闭，检测到错误写入，并且可以确定劣质商品。

2. 发明专利

JPS5956284A Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：JPS5956284A
公开(公告)日：1984-03-31
申请号：JP16491182
申请日：1982-09-24
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： OOUCHI YOSHIAKI , ISHIHARA MASAMICHI , MATSUMOTO TETSUO , MIYAZAWA KAZUYUKI
IPC分类号： G11C11/401 , G11C7/00 , G11C7/10 , G11C8/04
CPC分类号： G11C7/10 , G11C7/1033 , G11C8/04
摘要： PURPOSE: To form a semiconductor storage device provided with the mode, where data consisting of plural bits is read and written in series, and the mode where data is read and written in one-bit units.
CONSTITUTION: A 256k-bit memory cell array 1 is substituted with four divided 1M-bit memory mats 1aW1d, and the first pin is used as an address A
s , and the circuit is operated in the nibble mode. Thus, extension up to 1M bits is possible easily with the same design idea as a 256k-bit RAM without rearranging an address decoder 7 in a 16-pin package.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：形成具有模式的半导体存储装置，其中由多个比特组成的数据被串行读取和写入，并且以一位为单位读取和写入数据的模式。构成：256k位存储单元阵列1被四个分开的1M位存储器垫1a-1d代替，第一个引脚用作地址As，电路以半字节模式工作。因此，使用与256k位RAM相同的设计思想，可以容易地扩展到1M位，而无需将16位封装中的地址解码器7重新排列。

3. 发明专利

JPS6129488A Dynamic ram 失效
标题翻译：动态RAM
公开(公告)号：JPS6129488A
公开(公告)日：1986-02-10
申请号：JP14956084
申请日：1984-07-20
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： MATSUURA NOBUMI , MIYAZAWA KAZUYUKI , YANAGISAWA KAZUMASA
IPC分类号： G11C11/407 , G11C11/34
摘要： PURPOSE: To speed up further a high speed action and to improve an action margin by controlling the timing when the selection level of a word line is raised at a high level more than a power source voltage by means of a word line selection/activation circuit for consisting of a circuit similar to an address decoder.
CONSTITUTION: A memory cell for storing information is constituted of an information storing capacitor and an address selecting MOSFET, and selected by an address decoder R-DCR2. Synchronizing with a selecting action, an address decoder R-DCR1 constituted of circuits similar to said decoder R-DCR2 operates as an activating circuit. With the supply of an address signal, a word line selection timing signal ϕx is transmitted from a node between FETs Q39 and Q40, and its voltage is raised at a high level more than a power source V
cc of the signal ϕx by inverter circuits 1V2W1V5 serially connected to a bootstrap CB. Thus an RAM can act at a high speed, and simultaneously its action margin can be improved.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过字线选择/激活电路，当字线的选择电平升高到高于电源电压的高电平时，通过控制定时来加速进一步的高速动作并提高动作余量用于由地址解码器类似的电路组成。构成：用于存储信息的存储单元由信息存储电容器和地址选择MOSFET构成，并由地址解码器R-DCR2选择。与选择动作同步，由与解码器R-DCR2类似的电路构成的地址解码器R-DCR1作为激活电路进行动作。通过提供地址信号，从FET Q39和Q40之间的节点发送字线选择定时信号phix，并且其电压比反相器电路1V2-的信号phix的电源Vcc高出高电平， 1V5串联连接到自举CB。因此，RAM能够以高速行动，同时可以提高其动作余量。

4. 发明专利

JPS59210591A Dynamic memory 失效
标题翻译：动态记忆
公开(公告)号：JPS59210591A
公开(公告)日：1984-11-29
申请号：JP8274783
申请日：1983-05-13
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： KEMIZAKI KANEHIDE , MIYAZAWA KAZUYUKI , MATSUURA NOBUKI
IPC分类号： G11C11/409 , G11C11/34 , G11C11/401
CPC分类号： G11C11/34
摘要： PURPOSE:To facilitate test and appraisal and simplify initializing by providing a change-over circuit in input/output route of signal of a pair of complementary data lines and changing common data lines of true system and bar system automatically responding to proper address signal. CONSTITUTION:An intermediate change-over circuit 7 of common data lines CD, -CD consists of MOSFETQ11-Q14, and is on/off controlled receiving internal address signals ax1, -ax1 from an address buffer circuit 2 to the gate. A memory array 1 and an X decoder circuit 3 are so constituted that when internal address signal ax1 is high level, memory cell of D side of data line is selected, and when the signal -ax1 is high level, memory cell of -D side of data line is selected. Accordingly, reading and writing of memory cell of -D side of data line are made entirely in similar way with that of memory cell of D side of data line.
摘要翻译：目的：通过在一对互补数据线的信号的输入/输出路径中提供转换电路并改变真实系统和条形系统的公共数据线，自动响应正确的地址信号，便于测试和评估并简化初始化。构成：公共数据线CD，-CD的中间转换电路7由MOSFETQ11-Q14组成，并且被接通/断开控制，从地址缓冲电路2接收到内部地址信号ax1，-ax1到门。存储器阵列1和X解码器电路3被构造成当内部地址信号ax1为高电平时，选择数据线的D侧的存储单元，并且当信号-ax1为高电平时，-D侧的存储单元的数据线被选中。因此，数据线的-D侧的存储单元的读取和写入完全与数据线的D侧的存储单元的读取和写入完全相同。

5. 发明专利

JPH0935486A SEMICONDUCTOR NONVOLATILE MEMORY AND COMPUTER SYSTEM EMPLOYING IT 失效
公开(公告)号：JPH0935486A
公开(公告)日：1997-02-07
申请号：JP17524195
申请日：1995-07-11
申请人： HITACHI LTD
发明人： TANAKA TOSHIHIRO , KATO MASATAKA , KIMURA KATSUTAKA , OSHIMA KAZUYOSHI , MIYAZAWA KAZUYUKI
IPC分类号： G11C17/00 , G11C16/02 , G11C16/06 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To obtain a semiconductor nonvolatile memory in which noise resistance and disturb resistance can be enhanced through a reciprocal bit line/sense latch system by matching the layout of sense latch circuit and the pitch of bit line of memory cell. SOLUTION: An EEPROM is constituted of a plurality of memory mats comprising transistors having electrically rewritable threshold value wherein two sense latch circuits SL1-SLn are disposed on the opposite sides of respective memory mats for two bit lines B1-Bn. Data can be inputted/outputted for the memory mat from the opposite sides thereof through a column gate array circuit connected with sense latch circuits SL1-SLn. Read and verify operations are carried out based on the parity of bit lines B1-Bn and flush write operation is carried out regardless of the parity of bit lines B1-Bn.

6. 发明专利

JPH0778497A TESTING METHOD FOR DYNAMIC RAM 失效
公开(公告)号：JPH0778497A
公开(公告)日：1995-03-20
申请号：JP8128694
申请日：1994-04-20
申请人： HITACHI LTD
发明人： MIYAZAWA KAZUYUKI , SHIMOHIGASHI KATSUHIRO , ETO JUN , KIMURA KATSUTAKA
IPC分类号： G01R31/28 , G01R31/3185 , G11C11/401 , G11C29/00 , G11C29/34
摘要： PURPOSE:To realize the shortening of a testing time without increasing external terminals by a combination in which a row address strobe signal, a column address strobe signal and a write enabling signal are combined and which is not present in a normal mode. CONSTITUTION:In a timming when the row address strobe signal RASB is fallen from a high level to a low level, the column address strobe signal CASB and the write enabling signal WEB are turned to the low level. In this way, an operating mode is identified in a timming generating circuit TG and a high level signal is supplied to a latching circuit FF. In the latching circuit, the circuit is set by the signal to make a test signal TE to be the high level and testing circuits of the output side and input side included in multiplexers MPX1, 2 and data outputting circuit DOB are made to be in operating states. Thus, the starting-up/releasing of a testing mode is made possible without increasing numbers of external control signals.

7. 发明专利

JPH0669404A SEMICONDUCTOR MOUNTING DEVICE 失效
公开(公告)号：JPH0669404A
公开(公告)日：1994-03-11
申请号：JP22125292
申请日：1992-08-20
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： TARUISHI TOSHINORI , MAEDA TOSHIO , NAKAMOTO TOSHIHIRO , MIYAZAWA KAZUYUKI
IPC分类号： H01L23/50 , H05K1/18 , H05K3/34
摘要： PURPOSE:To provide a semiconductor mounting device which enables surface mounting on both the surface and rear of a mounting board without any modification of product specifications. CONSTITUTION:The semiconductor mounting device 100 has each lead 30 branched into a first frame lead portion 30A and a second branch lead portion 30B, and a first electrical contact portion 31 and a second electrical contact portion 32 are provided in the first and second branch lead portions 30A and 30B, respectively. For surface mounting on the surface 200a of a mounting board 200, the first electrical contact portion 31 is put in contact with a surface electrode portion 210. For surface mounting on the rear 200b, the second electrical contact portion 32 is put in contact with a rear electrode portion 220. In addition, the first and second electrical contact portions 31 and 32 may be provided in lead 30 by bending the lead 30 in the shape of a ring or making the lead into a multilayer lamination structure or three-dimensional structure, instead of forking the lead 30 into two branches.

8. 发明专利

JPH04345998A MEMORY DEVICE 失效
公开(公告)号：JPH04345998A
公开(公告)日：1992-12-01
申请号：JP11988791
申请日：1991-05-24
申请人： HITACHI LTD
发明人： NIWA AKIHIRO , KOBAYASHI YUTAKA , AKIYAMA NOBORU , YOKOYAMA YUJI , MIYAZAWA KAZUYUKI
IPC分类号： G11C11/413 , G11C11/401 , G11C29/00 , G11C29/04
摘要： PURPOSE:To attain a redundant circuit and its system which never extremely increase the area end the power consumption compared with a conventional redundant circuit system and also eliminate the access time delay caused by the relief of the defect of a word line. CONSTITUTION:In e RAM including plural memory mats 11 consisting of plural memory cells and redundant memory cells, the redundant word line of a certain memory mat is provided to another memory mat. In a non-relief state, only a word line has a rise for output of the data. When a defective word line is relieved, this defective word line and the redundant word line have the rises in the different mats and the data on both lines ere transmitted to a data line 12. A switch 14 is controlled and only the line 12 of the mat including a redundant word line is connected to 8 sense amplifier 15. Thus the data are amplified. Furthermore a rewriting amplifier is also switched and only the data on the redundant word line are written again. Thus the word line can be relieved with no access delay.

9. 发明专利

JPH04205877A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH04205877A
公开(公告)日：1992-07-28
申请号：JP32939490
申请日：1990-11-30
申请人： HITACHI LTD
发明人： NAKAMURA MASAYUKI , MIWA HITOSHI , OTA TATSUYUKI , NAKAI KIYOSHI , MIYAZAWA KAZUYUKI
IPC分类号： G11C11/401 , G11C11/403 , G11C11/407 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To eliminate the influence of compensation bit line selecting operations to access time by performing the complementary bit line selecting operations of a bit line selection circuit prior to the word line selecting operations of a word line selection circuit. CONSTITUTION:A direct sense system is adopted by individually providing a complementary common data reading-out line CDR and complementary common data writing line CDW to a Bi.CM0S dynamic RAM, etc. In addition, an address non-multiplex system is adopted by supplying X-address signals AXo-AXi and Y-address signals AYo-AYi from individual address input terminals and, at the same time, complementary bit line selecting operations are performed prior to word line selecting operations. Accordingly, the progress of the readout operations from a designated memory cell is transmitted to the complementary common data reading-out line, namely, to a main amplifier without any waiting time and without being destroyed by the complementary bit line selecting operations. Therefore, a semiconductor storage device the access time of which does not receive any influence form a complementary bit line can be obtained.

10. 发明专利

JPH04168692A NONINVERTED BUFFER AND SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH04168692A
公开(公告)日：1992-06-16
申请号：JP29372790
申请日：1990-11-01
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： YOKOYAMA YUJI , MIYAZAWA KAZUYUKI , MIWA HITOSHI , WADA SHOJI
IPC分类号： G11C11/409 , G11C7/10 , G11C8/06 , G11C11/417 , H03K19/013 , H03K19/0175 , H03K19/0944
摘要： PURPOSE:To make the operating speed of a noninverted buffer device faster by reducing the total number of the logical stages of the buffer device by integrating the plurality of logical stages of input buffer circuits constituting the buffer device. CONSTITUTION:An n- and p-type MOS transistors Q32 and Q31 are connected in parallel with each other between the base and collector of a bipolar transistor Tr31 and turning on/off of the transistors Q32 and Q31 are respectively controlled by means of the inverted and noninverted signals of input digital signals. The base current of the transistor Tr31 is supplied mainly from the transistor Q31 when the voltage across the gate and source of the transistor Tr31 is high and from the transistor Q32 when the voltage is low. Accordingly, the transistor Tr31 can always make a sufficient amount of collector current to flow, since a sufficient amount of the base current is always supplied to the transistor Tr31. Therefore, a noninverted buffer device which has one logical stage and a high operating speed can be obtained.

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