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21. 发明专利

JPH07187765A INSULATING PORCELAIN, ITS PRODUCTION PROCESS AND MULTILAYERED WIRING BASE PLATE 失效
公开(公告)号：JPH07187765A
公开(公告)日：1995-07-25
申请号：JP33079393
申请日：1993-12-27
申请人： KYOCERA CORP
发明人： YONEKURA HIDETO , HAMANO SATOSHI
IPC分类号： C04B35/18 , C04B35/19 , H05K1/03 , H05K3/46
摘要： PURPOSE:To produce an insulating porcelain of low cost which can be sintered at lowered temperatures (900 to 1,050 deg.C) and can employ copper, as an electric conductor without using a natural source mineral having high alpha-counts which gives adverse effect on devices such as IC. CONSTITUTION:This porcelain is composed of 35 to 60wt.% of SiO2, 20 to 53wt.% of Al2O3, 1 to 15wt.% of at least one of MgO and CaO and 1 to 10wt.% of at least two of Na2O, K2O and Li2O in terms of wt.% of respective oxides.

22. 发明专利

JPH06300465A BAKING JIG FOR GLASS-CERAMIC SUBSTRATE AND PRODUCTION THEREOF USING THE BAKING JIG 失效
公开(公告)号：JPH06300465A
公开(公告)日：1994-10-28
申请号：JP8740793
申请日：1993-04-14
申请人： KYOCERA CORP
发明人： HAMANO SATOSHI , KINOSHITA SHOWA
IPC分类号： C04B35/64 , C04B35/638 , F27D3/12 , H05K3/46
摘要： PURPOSE:To provide a baking jig which can remove organic components from a sintering body and carry them away to outside via a porous ceramic plate and a production method wherein the baking jig and a sintered body can be easily separated. CONSTITUTION:The baking jig is provided with a ceramic made frame 11 which receives in its interior a sheet-like molding 17 having the green sheets of glass- ceramic composition printed with a conductive paste and laminated together and a pair of gas-permeable porous ceramic plates 13 and 15 for pressing the molding 17 from above and below. The glass-ceramic substrate is produced by a method wherein a baking operation is performed while the molding 17 is being pressed by the porous ceramic plates 13 and 15 from above and below, with the mold release materials 19 made of the green sheet containing the ceramic particles having little wettability to glass at a temperature not above baking temperature and of slurry interposed between the frame 11, the porous ceramic plates 13 and 15 and the molding 17.

23. 发明专利

JPH0360443A LOW-TEMPERATURE CALCINED GLASS CERAMIC BODY 失效
公开(公告)号：JPH0360443A
公开(公告)日：1991-03-15
申请号：JP19782089
申请日：1989-07-28
申请人： KYOCERA CORP
发明人： EMURA HIDEO , HAMANO SATOSHI , ONIZUKA KATSUHIKO
IPC分类号： C03C8/14 , C03C14/00
摘要： PURPOSE:To obtain a low-temp. calcined glass ceramic body which is excellent in mechanical strength and low in thermal expansion coefficient and dielectric constant by blending the specified amount of alumina, quartz and cordierite with borosilicate glass powder and calcining the mixture at the specified temp. CONSTITUTION:Each powder of alumina, quartz and cordierite is blended with borosilicate glass powder. The blending rate is regulated to the rate wherein a glass ceramic body obtained by calcining incorporates 8-18wt.% alumina, 8-17wt.% quartz and 13-25wt.% cordierite and the balance borosilicate glass as a crystalline phase. Then the mixed powder is granulated and molded. This molded body is calcined at 900-1050 deg.C to produce the low-temp. calcined glass ceramic body. The thermal expansion coefficient of the obtained sintered body is the same degree as the thermal expansion coefficient of silicon constituting the element of a semiconductor integrated circuit. This sintered body is preferably utilized as an insulated base body such as a multilayer distribution base plate with the element of the semiconductor integrated circuit placed thereon.

24. 发明专利

JP2004327735A Method for manufacturing low-temperature baked multilayer ceramic wiring board 有权
标题翻译：制造低温多层陶瓷接线板的方法
公开(公告)号：JP2004327735A
公开(公告)日：2004-11-18
申请号：JP2003120763
申请日：2003-04-24
申请人： Kyocera Corp , 京セラ株式会社
发明人： TOMISAKO MASAHIRO , NAGAE KENICHI , NISHIURA TAKASUKE , HAMANO SATOSHI
IPC分类号： H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a low-temperature-baked multilayer ceramic wiring board, capable of increasing the degrees of freedom of a design of the wiring circuit board and a layer structure of an insulating layer with hardly constraints about the layer structure of the several insulating layers, having a different pattern shape of the wiring circuit layer arranged on the layer body and contraction behaviour.
SOLUTION: Warpage in the wiring board occurring with a mixture of several type of insulating layers 45, having different arrangement rate or contraction behaviour of the wiring circuit layers 35 of the low-temperature-baked multilayer ceramic wiring board comprising a plurality of insulating layers 31, can be suppressed by controlling the amount of glass contained in a holding sheet 51 laminated on the surface and the rear surface of the low-temperature-baked ceramic laminate.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种制造低温烧结多层陶瓷布线板的方法，其能够增加布线电路板的设计的自由度和几乎绝缘层的层结构关于布置在层体上的布线电路层的不同图案形状和收缩行为的几个绝缘层的层结构的限制。解决方案：由具有不同布置速度或收缩特性的几种类型的绝缘层45的混合物而发生的布线板的翘曲，该低温烧结多层陶瓷布线板包括多个可以通过控制层叠在低温烘焙陶瓷层叠体的表面和背面上的保持片材51中所含的玻璃的量来抑制绝缘层31。版权所有（C）2005，JPO＆NCIPI

25. 发明专利

JP2003224155A SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 审中-公开
公开(公告)号：JP2003224155A
公开(公告)日：2003-08-08
申请号：JP2002020156
申请日：2002-01-29
申请人： KYOCERA CORP
发明人： KIMURA TETSUYA , SHIGEOKA TOSHIAKI , HAMANO SATOSHI , TAMI YASUHIDE
IPC分类号： H01L23/12 , H01L21/56
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device of superior mounting reliability that is connected by a flip chip connecting method, and a method for manufacturing it. SOLUTION: A multilayer distributing board 1 comprises a plurality of metalized wiring layers 21 and a via hole conductor 22 at least on the surface and/or inside of a ceramic insulating substrate 19. A semiconductor element 7 provided with a connecting electrode 5 is mounted on the principal surface 2 of the multilayer distributing board 1. The metalized wiring layer 21 of the multilayer distributing board 1 is electrically connected to the connecting electrode 5 of the semiconductor element 7. A gap 9 between the multilayer distributing board 1 and the semiconductor element 7 is filled with a filler 11. In this semiconductor device constituted in such a manner that the pulse duty factor of an area of a void 23 in the principal surface 2 of the multilayer distributing board 1 where the filler 11 is applied is at least 8% or more. COPYRIGHT: (C)2003,JPO

26. 发明专利

JP2003078245A Method of manufacturing multilayer wiring substrate 审中-公开
标题翻译：制造多层布线基板的方法
公开(公告)号：JP2003078245A
公开(公告)日：2003-03-14
申请号：JP2001262463
申请日：2001-08-30
申请人： Kyocera Corp , 京セラ株式会社
发明人： KIMURA TETSUYA , TAMI YASUHIDE , SHIGEOKA TOSHIAKI , HAMANO SATOSHI
IPC分类号： H05K3/46 , H01L23/12
摘要： PROBLEM TO BE SOLVED: To stably control contraction in planar directions while preventing generation of cracks or delamination in the manufacturing of a wiring substrate which uses glass ceramics for an insulating substrate on which a wiring circuit layer formed of a metal foil is formed on the surface of the substrate. SOLUTION: This method of manufacturing a multilayer wiring substrate is constituted such that a wiring circuit layer 3 composed of metal foil is formed on the surface of a green sheet 1 which contains glass powder and inorganic filler powder, a plurality of the green sheets 1 are laminated, and the laminated body is fired at a temperature lower than the melting point of the wiring circuit layer 3 while suppressing contraction in planar directions. Tensile strength based on JIS K625 of the green sheets is adjusted to be 2000-5000 Kpa by varying the filling ratio, and kinds and added amounts of the organic binders.
摘要翻译：要解决的问题：为了稳定地控制平面方向的收缩，同时防止在使用玻璃陶瓷制造的布线基板的制造中产生裂纹或分层，所述布线基板在其上形成有由金属箔形成的布线电路层的绝缘基板的基底。解决方案：制造多层布线基板的方法是这样构成的：在包含玻璃粉末和无机填料粉末的生片1的表面上形成由金属箔构成的布线电路层3，多个生片1 并且层叠体在低于布线电路层3的熔点的温度下烧制，同时抑制平面方向的收缩。通过改变填充率以及有机粘合剂的种类和添加量，将生片的JIS K625的拉伸强度调整为2000〜5000Kpa。

27. 发明专利

JP2003046239A Multilayer wiring board and method of manufacturing it 审中-公开
标题翻译：多层接线板及其制造方法
公开(公告)号：JP2003046239A
公开(公告)日：2003-02-14
申请号：JP2001228026
申请日：2001-07-27
申请人： Kyocera Corp , 京セラ株式会社
发明人： KIMURA TETSUYA , HAMANO SATOSHI , SHIGEOKA TOSHIAKI , TAMI YASUHIDE
IPC分类号： H05K1/09 , C04B41/90 , H05K3/38 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a multilayer wiring board which is superior in dimensional accuracy and equipped with a wiring layer that is bonded to an insulating board with high strength after baking, has no problem about an external appearance such as a spread of plating, and is low in specific resistance. SOLUTION: A multilayer wiring board A is composed of an insulating board 10 of glass ceramic and a wiring layer 3 of high-purity metal conductor which contains 99.5 wt.% or above copper and is formed on the surface of the wiring board A and/or inside it, and a diffusion layer 8 containing at least one element out of Sn and Zn is formed as thick as 1 to 40 μm on the surface of the wiring layer 3 coming into contact with the insulating board 10.
摘要翻译：要解决的问题：为了提供尺寸精度优异并且配备有在烘烤后与强度高的绝缘基板接合的布线层的多层布线板，对镀层的扩展等外观没有问题，电阻率低。解决方案：多层布线板A由玻璃陶瓷的绝缘板10和含有99.5重量％以上的铜的高纯度金属导体的布线层3构成，形成在布线基板A的表面和/ 或其内部，并且在与绝缘板10接触的布线层3的表面上形成厚度为1〜40μm的含有Sn和Zn中的至少一种元素的扩散层8。

28. 发明专利

JP2002329970A METHOD OF MANUFACTURING MULTILAYER WIRING BOARD 失效
公开(公告)号：JP2002329970A
公开(公告)日：2002-11-15
申请号：JP2001131684
申请日：2001-04-27
申请人： KYOCERA CORP
发明人： KIMURA TETSUYA , HAMANO SATOSHI , SHIGEOKA TOSHIAKI , TAMI YASUHIDE , NAGAE KENICHI
IPC分类号： C04B37/02 , C04B35/00 , C04B35/495 , H01L23/12 , H01L23/14 , H01L23/15 , H05K3/20 , H05K3/38 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To avoid the defective transfer of a wiring circuit layer when the wiring circuit layer is formed by transfer from a transfer sheet onto a surface of a ceramic green sheet, and to suppress the generation of delamination or the like of the wiring circuit layer even after being baked. SOLUTION: In the method for manufacturing a multilayer wiring board, a transfer sheet 5 having a wiring circuit layer formed on a surface of the transfer sheet and made of high-purity metal 3 containing 99.5 weight % or more of metal is prepared; the wiring circuit layer is transferred from the transfer sheet 5 onto a surface of a ceramic green sheet 1; a plurality of green sheets 1a, 1b and 1c are laminated thereon; and then baked at a temperature lower than the melting point of the metal 3 of the wiring circuit board. A bonding layer 4 having a thickness of 1-15 μm and containing such organic resin as acrylics resin excellent in a pyrolytic property is formed on a surface of the wiring circuit layer 3 on the transfer sheet, and the wiring circuit layer 3 is transferred onto the green sheet via the bonding layer 4.

29. 发明专利

JP2002255645A PORCELAIN FIRED AT LOW TEMPERATURE AND WIRING BOARD USING THE SAME 失效
公开(公告)号：JP2002255645A
公开(公告)日：2002-09-11
申请号：JP2001053180
申请日：2001-02-27
申请人： KYOCERA CORP
发明人： HAMANO SATOSHI , TOMISAKO MASAHIRO , KODAMA KAZUYOSHI
IPC分类号： C04B35/00 , C04B35/16 , C04B35/495 , H01L23/12 , H01L23/15 , H05K1/03 , H05K3/24 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a porcelain fired at a low temperature, which is dense even when it is sintered at a temperature of =7 wt.%, expressed in terms of ZnO, based on the total weight of the porcelain, and further an oxide of at least one selected from the oxides of Fe, Co and Ni in an amount of 0.05 to 10 wt.%, expressed in terms of their oxides: FeO, CoO or NiO, based on the total weight of the porcelain. A package (wiring board) for accommodating a semiconductor device is fabricated by using the porcelain above as an insulating board 2 and forming the conductive wiring layer 3 on the surface and/or at the inside of the insulating board 2.

30. 发明专利

JP2002171043A CERAMIC WIRING BOARD 失效
公开(公告)号：JP2002171043A
公开(公告)日：2002-06-14
申请号：JP2000363694
申请日：2000-11-29
申请人： KYOCERA CORP
发明人： SHIGEOKA TOSHIAKI , HAMANO SATOSHI , TOMISAKO MASAHIRO , KODAMA KAZUYOSHI , KIMURA TETSUYA
IPC分类号： H05K1/11
摘要： PROBLEM TO BE SOLVED: To improve connection reliability between via hole conductor, formed by a method wherein the inside of a via hole is filled with a metallized paste, and a wiring circuit layer constituted of a metal foil. SOLUTION: A wiring board is provided with a ceramic-insulating board 1, the wiring circuit layer 2 which is formed on a surface of the insulating board 1 and constituted of the metal foil, and the via hole conductor 3 formed by a method, where the inside of the via hole of the insulating board 1 is filled with metal powder. In the wiring board, the via hole conductor 3 and the wiring circuit layer 2 constituted of the metal foil are connected via a metallized layer 4, formed by baking the metallized paste.

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