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1. 发明专利

JP2008177334A Electronic component mounting board 审中-公开
标题翻译：电子元件安装板
公开(公告)号：JP2008177334A
公开(公告)日：2008-07-31
申请号：JP2007008998
申请日：2007-01-18
申请人： Kyocera Corp , 京セラ株式会社
发明人： YONEKURA HIDETO
IPC分类号： H01L23/13 , H01L21/52 , H01L23/12 , H01L23/15
CPC分类号： H01L24/83 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83 , H01L2924/14 , H01L2924/351 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide an electronic component mounting board which allows an electronic component to be firmly bonded and fixed on a mounting portion via an adhesive even if a metallized layer coated with a gold plating layer is so formed as to cover the mounting portion, making it possible to easily manufacture a reliable electronic device. SOLUTION: The electronic component mounting board 9 is formed with the metallized layer 2 coated with the gold plating layer 7 on the mounting portion 1a of an insulating substrate 1 and has the electronic component 5 mounted on the metallized layer 2 and fixed thereon via the adhesive 6. In this board 9, the metallized layer 2 contains a ceramic powder 4 part of which is exposed on the surface of the gold plating layer 7. The ceramic powder 4 part of which is exposed on the surface of the gold plating layer 7 reinforces the adhesive strength of the adhesive 6, making it possible to firmly bond the electronic component 5 on the mounting portion 1a via the adhesive 6. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种电子部件安装板，其允许电子部件通过粘合剂牢固地结合并固定在安装部分上，即使涂覆有镀金层的金属化层形成为覆盖安装部分，使得可以容易地制造可靠的电子设备。解决方案：电子部件安装板9在绝缘基板1的安装部分1a上形成涂覆有镀金层7的金属化层2，并且安装在金属化层2上并固定在其上的电子部件5 在该板9中，金属化层2含有4份暴露在镀金层7的表面上的陶瓷粉末。其中一部分暴露在镀金表面上的陶瓷粉末4 层7增强了粘合剂6的粘合强度，使得可以通过粘合剂6将电子部件5牢固地粘合在安装部分1a上。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2002324874A WIRING BOARD 失效
公开(公告)号：JP2002324874A
公开(公告)日：2002-11-08
申请号：JP2001128209
申请日：2001-04-25
申请人： KYOCERA CORP
发明人： YONEKURA HIDETO , MATSUDERA HIROSHI
IPC分类号： H05K1/09 , H01L23/12 , H01L23/13 , H01L23/14 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To resolve a problem where the distance between adjacent wiring layers becomes shorter and thus the reliability of electrical insulation between the wiring layers is low. SOLUTION: In the wiring board 5 where a plurality of internal wiring layers 2 are formed inside an insulating substrate 1 and a plurality of connection pads 3 to be electrically connected with the internal wiring layers 2 are formed on its surface, the internal wiring layers 2 are formed using tungsten and/or molybdenum and copper and the connection pads 3 are formed using tungsten and/or molybdenum and an iron group metal.

3. 发明专利

JP2000022017A CERAMIC WIRING SUBSTRATE AND PACKAGE STRUCTURE THEREOF 失效
公开(公告)号：JP2000022017A
公开(公告)日：2000-01-21
申请号：JP18894098
申请日：1998-07-03
申请人： KYOCERA CORP
发明人： KOKUBU MASAYA , AZUMA MASAHIKO , YONEKURA HIDETO , NAGATA KOICHI
IPC分类号： H01L23/04 , H01L23/08
摘要： PROBLEM TO BE SOLVED: To provide high reliable ceramic wiring substrate capable of sustaining firmly and stably connected state when a wiring substrate assuming a glass ceramics as an insulating substrate is packaged on an outer circuit substrate whereon a wiring layer is coat-formed on the surface of the insulating substrate containing organic resin by brazing process and the package structure thereof. SOLUTION: In the package structure of a ceramic wiring substrate wherein a ceramic wiring substrate A provided with an insulating substrate 1 made of a glass ceramics, a wiring circuit layer 4 made of a low resistant metal formed on the surface or inside the insulating substrate 1 and a plurality of connecting pads 5 formed on the bottom face of the insulating substrate 1 is electrically connected to an outer circuit substrate B wherein wiring layers 8 are coat-formed on the surface of an insulating base substrate 7 containing organic resin between the connecting pads 5 and the wiring layers using the connecting terminals 6 made of spherical wax material. The pad diameter x of the connecting pads 5 is formed to be 55-65% of the intercentral distance y. Furthermore, it is recommended that the thermal expansion difference between the insulating substrate 1 and the insulating base substrate 7 may be 1-8 ppm/ deg.C.

4. 发明专利

JPH11284320A MOUNTING STRUCTURE OF WIRING BOARD 失效
公开(公告)号：JPH11284320A
公开(公告)日：1999-10-15
申请号：JP8218298
申请日：1998-03-27
申请人： KYOCERA CORP
发明人： YONEKURA HIDETO , AZUMA MASAHIKO , YAMAGUCHI KOICHI , FURUKUBO YOJI , NAGAE KENICHI
IPC分类号： H05K3/34 , H01L21/60 , H05K1/18 , H05K3/36
摘要： PROBLEM TO BE SOLVED: To maintain a stable connecting condition for a long time to improve the reliability by providing Cu-contg. regions on the braze zone end at least at a wiring conductor or connecting electrode side. SOLUTION: A semiconductor package and electric circuit board B constitute a main part, the semiconductor package A is composed of an insulation board 1, cover, metallized wiring layer 3 and connecting electrodes 4, the connecting electrodes 4 are printed with a Cu-contg. solder paste to form a Cu-contg. low-m. p. solder layer 9 to be Cu-contg. regions and printed with a solder past not contg. Cu to form a low-m. p. solder layer 8 not contg. Cu to adhere solder balls 7, a Cu-contg. low-m. p. solder layer 12 and low-m. p. solder layer 13 not contg. solder are formed on the wiring conductors 11 surfaces of the electric circuit board B, he solder balls 7 of the semiconductor package are set to butt the low-m. p. solder layer 13 of the electric circuit board B, heated to fuse, thereby mounting the semiconductor package A on the electric circuit board B.

5. 发明专利

JPH1117065A WIRING BOARD, PACKAGE FOR ACCOMMODATION OF SEMICONDUCTOR ELEMENT USING THE WIRING BOARD, AND MOUNTING STRUCTURE THEREOF 失效
公开(公告)号：JPH1117065A
公开(公告)日：1999-01-22
申请号：JP17258597
申请日：1997-06-27
申请人： KYOCERA CORP
发明人： YONEKURA HIDETO , YAMAGUCHI KOICHI , HAMADA NORIAKI , KIMURA TETSUYA , FURUKUBO YOJI
IPC分类号： H05K3/34 , H01L23/14 , H05K1/03 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a wiring board which can realize simultaneous burning of metallized wiring layers, can have a high thermal expansion coefficient and a low dielectric dissipation factor, can be manufactured inexpensively with a high quality, and can be stable in electrical connection and high in reliability when mounted to an external electric circuit board. SOLUTION: In a package A for accommodation of a wiring board or a semiconductor element in which a metallized wiring layer 3 made of e.g. Cu is provided on or in an insulating substrate 1, the insulating substrate 1 contains a total of 5-30 weight % of alkaline metal oxides of two selected from the group of Li2 O, Na2 O and K2 O. The substrate is made of a sintered material having a linear thermal expansion coefficient of 8-18 ppm/ deg.C at 40-400 deg.C obtained by burning a molding material which contains 20-80 volume % of alkaline silicon glass having a yield point of 400-800 deg.C and 80-20 volume % of filler including metal oxide having a linear thermal expansion coefficient of 6 ppm/ deg.C at 40-400 deg.C.

6. 发明专利

JPH10182239A PRODUCTION OF GREEN SHEET FOR CERAMIC SUBSTRATE 失效
公开(公告)号：JPH10182239A
公开(公告)日：1998-07-07
申请号：JP33869096
申请日：1996-12-18
申请人： KYOCERA CORP
发明人： YONEKURA HIDETO , KUMADAHARA HITOSHI , TAMI YASUHIDE , YAMAGUCHI KOICHI
IPC分类号： C04B35/622 , C04B35/632
摘要： PROBLEM TO BE SOLVED: To prevent gelation of slurry and deformation of a green sheet in the manufacture of the sheet containing a glass containing >=5wt.% alkali metal oxide. SOLUTION: The slurry is prepared by adding an acrylic resin having carboxyl group and a solvent into the glass powder containing >=5wt.% alkali metal oxide such as an alkali silica glass, a soda aluminum silicate glass or a powdery mixture of the glass power and a ceramic powder. In the manufacture of the green sheet for ceramic substrate by using the slurry and forming into a sheet like state, the slurry prevented from film forming property, excellent in dispensability and capable of obtaining the green sheet having excellent packing ratio is obtained by using a mixed solvent containing an aromatic solvent and an alcohol based solvent having a evaporation rate index of

7. 发明专利

JPH10135370A WIRING BOARD, PACKAGE FOR SEMICONDUCTOR ELEMENT AND MOUNTING STRUCTURE THEREOF 失效
公开(公告)号：JPH10135370A
公开(公告)日：1998-05-22
申请号：JP29042796
申请日：1996-10-31
申请人： KYOCERA CORP
发明人： YAMAGUCHI KOICHI , HAMADA NORIAKI , YONEKURA HIDETO , FURUKUBO YOJI , AZUMA MASAHIKO
IPC分类号： H05K1/03 , H01L23/12 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To enhance long term mounting stability for an external circuit board containing a high thermal expansion organic resin. SOLUTION: In a package A for wiring board or semiconductor element provided with a metallization layer 3 of Ag, for example, in an insulating substrate 1 or on the surface thereof, the insulating substrate 1 of a sintered body having coefficient of thermal expansion in the range of 8-18ppm/ deg.C at 40-400 deg.C produced by sintering a molding containing 20-80vol.% of glass powder having coefficient of thermal expansion higher than 6ppm/ deg.C at 40-400 deg.C after sintering, and 80-20vol.% of filter containing a metal oxide having coefficient of thermal expansion higher than 6ppm/ deg.C at 40-400 deg.C. It is mounted on an external circuit board B where a wiring conductor 11 is formed on the surface of an insulator 10 containing at least an organic resin and brazed through connection terminals 4.

8. 发明专利

JPH09129782A WIRING BOARD, SEMICONDUCTOR ELEMENT-HOUSING PACKAGE USING THE SAME, AND ITS MOUNTING STRUCTURE 失效
公开(公告)号：JPH09129782A
公开(公告)日：1997-05-16
申请号：JP28383295
申请日：1995-10-31
申请人： KYOCERA CORP
发明人： YAMAGUCHI KOICHI , HAMADA NORIAKI , YONEKURA HIDETO , AZUMA MASAHIKO , TAMI YASUHIDE , FURUKUBO YOJI
IPC分类号： H05K1/03 , H01L23/15 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To improve contact property of an insulating board by forming a sintered body having a specified coefficient of thermal expansion over a specified range of temperature by firing a compact which contains a specified range of percentage by volume of sodium aluminum silicate glass over a specified range of temperature and a specified range of percentage by volume of filler containing a metal oxide having a specified or higher coefficient of thermal expansion over a specified range of temperature. SOLUTION: A semiconductor element housing package A, including a sintered body having a coefficient of thermal expansion of 8-18ppm/ deg.C at 40-400 deg.C which is obtained by firing a compact containing, at a protruding point thereof containing SiO2 , Al2 O3 and Na2 O, 20-80% by volume of sodium aluminum silicate glass of 400-800 deg.C and 80-20% by volume of filler containing a metal oxide having a coefficient of thermal expansion not lower than 6ppm/ deg.C at 40-400 deg.C, is soldered and mounted as an insulating board 1 with a wiring conductor 8 on an external electric circuit board B via a connection terminal 4. Thus, reliability of contact property or the like of the metallization wiring onto the board B may be improved.

9. 发明专利

JPH08295558A GLASS-CERAMIC SINTERED COMPACT AND ITS MANUFACTURE 失效
公开(公告)号：JPH08295558A
公开(公告)日：1996-11-12
申请号：JP10370295
申请日：1995-04-27
申请人： KYOCERA CORP
发明人： TERASHI YOSHITAKE , YONEKURA HIDETO , HAMANO SATOSHI
IPC分类号： C04B35/16 , C04B35/48
摘要： PURPOSE: To produce a sintered compact which has high permittivity and high strength and is formed from a green compact that can be simultaneously sintered together with metallic wiring by using a green compact contg. at least Zr, Ca, Si, Al, Mg, Zn and B metallic elements for forming a sintered compact contg. ZrO2 crystal phases, spinel type crystal phases, anorthite type crystal phases and a glass phase. CONSTITUTION: In this manufacture, 30 to 70wt.% of SiO2 -Al2 O3 -MgO-ZnO-B2 O3 based glass and 70 to 30wt.% of the total amount in terms of oxide of Ca oxide and Zr oxide (optionally in the form of a compound consisting of them) which are used as filler components are mixed together to obtain a powdery mixture and an adequate amount of a binder is added to the powdery mixture and, thereafter, the resultant mixture is formed into a green compact. Then, the green compact is sintered in a non-oxidizing atmosphere at 800 to 950 deg.C for 0.1 to 5 hours to manufacture the objective sintered compact contg. ZrO2 crystal phases 1, spinel type crystal phases 2, anorthite type crystal phases 3 and a glass phase 5. To manufacture a wiring substrate by using this sintered compact, the above powdery mixture is formed into a green sheet for forming an insulating layer, and then, a wiring pattern is printed on the surface of the green sheet with a metallic paste by a screen process, and simultaneous sintering of the resultant wiring layer and the insulating layer is performed under the above sintering conditions.

10. 发明专利

JPH07187765A INSULATING PORCELAIN, ITS PRODUCTION PROCESS AND MULTILAYERED WIRING BASE PLATE 失效
公开(公告)号：JPH07187765A
公开(公告)日：1995-07-25
申请号：JP33079393
申请日：1993-12-27
申请人： KYOCERA CORP
发明人： YONEKURA HIDETO , HAMANO SATOSHI
IPC分类号： C04B35/18 , C04B35/19 , H05K1/03 , H05K3/46
摘要： PURPOSE:To produce an insulating porcelain of low cost which can be sintered at lowered temperatures (900 to 1,050 deg.C) and can employ copper, as an electric conductor without using a natural source mineral having high alpha-counts which gives adverse effect on devices such as IC. CONSTITUTION:This porcelain is composed of 35 to 60wt.% of SiO2, 20 to 53wt.% of Al2O3, 1 to 15wt.% of at least one of MgO and CaO and 1 to 10wt.% of at least two of Na2O, K2O and Li2O in terms of wt.% of respective oxides.

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