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1. 发明专利

JP2005159041A Method for manufacturing multilayer ceramic wiring board 审中-公开
标题翻译：制造多层陶瓷接线板的方法
公开(公告)号：JP2005159041A
公开(公告)日：2005-06-16
申请号：JP2003396130
申请日：2003-11-26
申请人： Kyocera Corp , 京セラ株式会社
发明人： NAGAE KENICHI , NISHIURA TAKASUKE
IPC分类号： C04B35/64 , H01L23/12 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a multilayer ceramic wiring board capable of obtaining a high dimensional accuracy even if a laminated body is burned in a continuous kiln. SOLUTION: In the method for manufacturing the multilayer ceramic wiring board, a conductive pattern 3 and a via hole conductor 2 are formed in a ceramic green sheet 1, a laminated body 4 obtained by laminating a plurality of desired ceramic green sheets 1 manufactured similarly is placed on a tray 5, the tray 5 is mounted on a movable belt, and a burning process is performed by passing it in an area heated at a desired temperature. A metal is spread inside the tray 5, and a dispersion ratio of the metal component is gradually reduced from a rear end side to a front end side with respect to a progress direction of the movable belt. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种即使层压体在连续窑中燃烧也能够获得高尺寸精度的多层陶瓷布线板的制造方法。解决方案：在多层陶瓷布线板的制造方法中，在陶瓷生片1中形成导电图案3和通孔导体2，层叠多个所需的陶瓷生片1 制造类似地放置在托盘5上，托盘5安装在可移动的带上，并且通过使其在加热到期望温度的区域中进行燃烧过程。在托盘5内部扩散金属，并且金属部件的分散比率相对于可动带的行进方向从后端侧逐渐减小到前端侧。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2004063812A Method of manufacturing multilayer wiring board 审中-公开
公开(公告)号：JP2004063812A
公开(公告)日：2004-02-26
申请号：JP2002220484
申请日：2002-07-29
申请人： Kyocera Corp , 京セラ株式会社
发明人： SUZUKI SHINICHI , NAKAO YOSHIHIRO , NAGAE KENICHI
IPC分类号： H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a multilayer wiring board which can reduce the transmission loss even if a high dielectric constant layer is arranged in the main board, and can reduce warpage.
SOLUTION: Between one main surface and the other main surface of this board, two kinds of low dielectric constant green sheets L1G, L2G and a high dielectric constant green sheet H1G are interposed so that the high dielectric constant green sheet H1G is arranged within the thickness of Z/2 from the other main surface, when the thickness of the laminated molded body between one main surface and the other main surface is defined as Z; the low dielectric constant green sheet L2G is arranged within the thickness of Z/2 from one main surface; and the low dielectric constant green sheet L2G and the high dielectric constant green sheet H1G are arranged so as to make contact with the low dielectric constant green sheet L1G at least with one surface of each of them. When shrinkage starting temperatures of the low dielectric constant green sheets L1G, L2G and high dielectric constant green sheet H1G are defined as T1, T2 and T3, the following relations are satisfied: T1>T3, T1>T2, and |T2-T3|≤5°C.
COPYRIGHT: (C)2004,JPO

3. 发明专利

JP2003101229A CERAMIC MULTILAYER WIRING BOARD AND ITS MANUFACTURING METHOD 审中-公开
公开(公告)号：JP2003101229A
公开(公告)日：2003-04-04
申请号：JP2001298546
申请日：2001-09-27
申请人： KYOCERA CORP
发明人： SUZUKI SHINICHI , NAKAO YOSHIHIRO , NAGAE KENICHI
IPC分类号： B32B18/00 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a ceramic multilayer wiring board in which a wring layer formed of a low permittivity ceramic layer is disposed near a chip, and a capacitor layer formed of a high permittivity ceramic layer is disposed on a rear surface side of the substrate and which does not have a warpage and to provide a method for manufacturing the same. SOLUTION: The ceramic multilayer wiring board comprises the low permittivity ceramic layer 5 and the high permittivity ceramic layer 7. The substrate satisfies t1

4. 发明专利

JP2003040670A High thermal expansion ceramic composition, high thermal expansion ceramic and its manufacturing method, and multilayer wiring substrate and its mounting structure 审中-公开
标题翻译：高热膨胀陶瓷组合物，高热膨胀陶瓷及其制造方法和多层布线基板及其安装结构
公开(公告)号：JP2003040670A
公开(公告)日：2003-02-13
申请号：JP2001228025
申请日：2001-07-27
申请人： Kyocera Corp , 京セラ株式会社
发明人： NAKAO YOSHIHIRO , NAGAE KENICHI , SUZUKI SHINICHI , FURUKUBO YOJI
IPC分类号： C04B35/14 , C04B35/195 , H01L23/15 , H05K3/46
CPC分类号： H01L2224/48091 , H01L2224/48227 , H01L2924/01012 , H01L2924/0102 , H01L2924/01046 , H01L2924/01057 , H01L2924/01078 , H01L2924/09701 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/15787 , H01L2924/16195 , H01L2924/19041 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To obtain a multilayer wiring substrate laminated with a high thermal expansion ceramic composed of a complex composition of glass containing BaO and a filler, excellent in low permittivity, in chemical resistance and in strength, and high permittivity layer using the ceramic, excellent in mounting reliability for a long term. SOLUTION: In the high thermal expansion multilayer wiring substrate, the metalized wiring layers 3 are arranged on surface and/or inside of the insulation substrate 1 which is composed of the low permittivity layers 1a and the high permittivity layer 1b. The low permittivity layers 1a are a composition composed of glass of 20-80 vol.% containing BaO of 5-60 wt.%, and inorganic filler of 20-80 vol.% which is containing a metallic oxide of 20-99 wt.%, the coefficient of linear expansion of which is >=6 ppm/ deg.C at 40-400 deg.C and codierite of 1-80 wt.%. The high thermal expansion ceramic whose coefficient of thermal expansion is 8-15 ppm/ deg.C, at firing temperature of 40-400 deg.C, and relative permittivity is
摘要翻译：要解决的问题：为了获得层叠有由包含BaO的玻璃和填料的复合组合物组成的高热膨胀陶瓷的多层布线基板，其具有优异的低介电常数，耐化学性和强度，以及使用陶瓷的高介电常数层，长期稳定可靠。解决方案：在高热膨胀多层布线基板中，金属化布线层3布置在由低介电常数层1a和高介电常数层1b组成的绝缘基板1的表面和/或内部。低介电常数层1a是由含有5-60重量％的BaO的20-80体积％的玻璃和20-80重量％的含有20〜99重量％的金属氧化物的无机填料构成的组合物。％，其线膨胀系数在40-400℃为> 6ppm /℃，1-80重量％的堇青石。通过焙烧该组合物，获得在烧制温度为40-400℃的热膨胀系数为8-15ppm /℃，相对介电常数为1的高热膨胀陶瓷为1。

5. 发明专利

JP2001342057A GLASS-CERAMICS SINTERED COMPACT AND MULTILAYERED WIRING BOARD USING THE SAME 失效
公开(公告)号：JP2001342057A
公开(公告)日：2001-12-11
申请号：JP2000161605
申请日：2000-05-31
申请人： KYOCERA CORP
发明人： NAGAE KENICHI , SUZUKI SHINICHI , NAKAO YOSHIHIRO , KOKUBU MASAYA , AZUMA MASAHIKO
IPC分类号： C04B35/16 , H01L23/12 , H01L23/15 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a glass-ceramics sintered compact which has excellent sintering performance, enables the firing together with a high temperature expanded glass-ceramics sintered compact and has high thermal expansion coefficient and high dielectric constant, and also provide a wiring board with built-in capacitor superior in mounting reliability to a printed circuit board in which an organic resin is used as an insulating material. SOLUTION: This glass-ceramics sintered compact comprises 50-70 vol.% of a glass component having a thermal expansion coefficient of 6-18×10-6/ deg.C at the temperatures of 40 to 400 deg.C, and 30-50 vol.% of filler components. The filler components include (a) lanthanum titanate, (b) titanates other than the component (a), and (c) zirconium-containing oxide. Another objective wiring board is obtained by using at least one layer of the glass-ceramics sintered compact having the thermal expansion coefficient of 8×10-6/ deg.C or more at the temperatures of 40 to 400 deg.C and the specific dielectric constant of 14 at 1 MHz as an inner layer of a multilayered wiring board, and forming the metallized electrodes on the upper and lower faces of the above inner layer to make a capacitor build in.

6. 发明专利

JP2001181023A SINTERED COMPACT OF GLASS CERAMIC, AND CIRCUIT BOARD 失效
公开(公告)号：JP2001181023A
公开(公告)日：2001-07-03
申请号：JP36502599
申请日：1999-12-22
申请人： KYOCERA CORP
发明人： NAKAO YOSHIHIRO , HAMADA NORIAKI , NAGAE KENICHI , FURUKUBO YOJI , TAMI YASUHIDE
IPC分类号： H05K1/03 , C04B35/16
摘要： PROBLEM TO BE SOLVED: To provide a sintered compact of glass ceramic and a circuit board using the sintered compact as an insulating substrate, capable of forming a moralized wiring layer of a metal such as Cu, Ag, or the like, due to the low temp. sintering of the compact, excellent in tenacity, strength properties, or the like, usable suitably for a circuit board package, or the like, mounting semiconductor elements, or the like. SOLUTION: This sintered compact is a glass ceramic sintered compact obtained by sintering a mixture of a glass with a ceramic filler and including crystal barium metasilicate having average aspect ration of >=3, and a circuit board using the sintered compact of glass ceramic as an insulating substrate is provided.

7. 发明专利

JP2001035963A WIRING BOARD FOR MOUNTING SEMICONDUCTOR ELEMENT AND MOUNTING STRUCTURE THEREOF 失效
公开(公告)号：JP2001035963A
公开(公告)日：2001-02-09
申请号：JP20818599
申请日：1999-07-22
申请人： KYOCERA CORP
发明人： NAGAE KENICHI , AZUMA MASAHIKO , TOKUMITSU YOSHITERU , YANO MASATO , NAKAO YOSHIHIRO
IPC分类号： H05K1/18 , H01L23/12 , H05K1/14
摘要： PROBLEM TO BE SOLVED: To sustain stabilized connecting state rigidly for a long term when a wiring board for semiconductor package is surface mounted on an external circuit board by forming a terminal electrode on the bottom face of a recess formed shallower on the central side of a wiring board. SOLUTION: A semiconductor element 5 is placed in a recess 1a made in the center of one major surface of a wiring board 1 and applied with a cover 2. A metallized wiring layer 3 is formed on the surface and in the wiring board 1 and the connection terminal 4 of a terminal electrode 3a is previously bonded to the other major surface of the wiring board 1. More specifically, the connection terminal 4 bonded to the terminal electrode 3a is formed on the bottom face in each of a large number of recesses 11 where the terminal electrode 3a is formed on the lower surface of the wiring board 1 in a BGA(ball grid array) type semiconductor package A. The recess 11 for forming the terminal electrode 3a is made shallow on the center 01 side on the lower surface of the wiring board 1 and made deep on the opposite side.

8. 发明专利

JPH11284320A MOUNTING STRUCTURE OF WIRING BOARD 失效
公开(公告)号：JPH11284320A
公开(公告)日：1999-10-15
申请号：JP8218298
申请日：1998-03-27
申请人： KYOCERA CORP
发明人： YONEKURA HIDETO , AZUMA MASAHIKO , YAMAGUCHI KOICHI , FURUKUBO YOJI , NAGAE KENICHI
IPC分类号： H05K3/34 , H01L21/60 , H05K1/18 , H05K3/36
摘要： PROBLEM TO BE SOLVED: To maintain a stable connecting condition for a long time to improve the reliability by providing Cu-contg. regions on the braze zone end at least at a wiring conductor or connecting electrode side. SOLUTION: A semiconductor package and electric circuit board B constitute a main part, the semiconductor package A is composed of an insulation board 1, cover, metallized wiring layer 3 and connecting electrodes 4, the connecting electrodes 4 are printed with a Cu-contg. solder paste to form a Cu-contg. low-m. p. solder layer 9 to be Cu-contg. regions and printed with a solder past not contg. Cu to form a low-m. p. solder layer 8 not contg. Cu to adhere solder balls 7, a Cu-contg. low-m. p. solder layer 12 and low-m. p. solder layer 13 not contg. solder are formed on the wiring conductors 11 surfaces of the electric circuit board B, he solder balls 7 of the semiconductor package are set to butt the low-m. p. solder layer 13 of the electric circuit board B, heated to fuse, thereby mounting the semiconductor package A on the electric circuit board B.

9. 发明专利

JPH08298380A MULTILAYER WIRING BOARD AND PACKAGE FOR SEMICONDUCTOR ELEMENT 失效
公开(公告)号：JPH08298380A
公开(公告)日：1996-11-12
申请号：JP10370195
申请日：1995-04-27
申请人： KYOCERA CORP
发明人： SAKAGUCHI ITSURO , NAGAE KENICHI , YOMO KUNIHIDE
IPC分类号： H05K3/46 , H01L23/08 , H05K1/00 , H05K1/03 , H05K1/16
摘要： PURPOSE: To obtain a multilayer wiring board having a capacitor part of stabilized characteristics, and a package for semiconductor element, by preventing the components of a highly dielectric layer from being diffused into an electrode layer or an insulator layer. CONSTITUTION: In the multilayer wiring board having a capacitor part 6 comprising a high dielectric layer 3 sandwiched by a pair of electrode layers 4, 5, and a package for semiconductor element, the high dielectric layer 3 is composed of a glass phase containing Al2 O3 particles, 5-95vol.% of zirconate particles, at least one kind of oxide of alkaline earth metal, rare earth element, Al and Si present at the grain boundary thereof and an oxide of Zr. An insulator layer is composed of a glass phase containing alumina particles, zirconate particles, at least one kind of oxide of alkaline earth metal, rare earth element, Al and Si and an oxide of Zr.

10. 发明专利

JP2013258372A Green sheet and wiring mother board 审中-公开
标题翻译：绿色板材和接线母板
公开(公告)号：JP2013258372A
公开(公告)日：2013-12-26
申请号：JP2012134932
申请日：2012-06-14
申请人： Kyocera Corp , 京セラ株式会社
发明人： NAGAE KENICHI
IPC分类号： H05K1/03 , H05K1/02
摘要： PROBLEM TO BE SOLVED: To provide a green sheet for manufacturing a wiring mother board in which deformation of a wiring board region is reduced by a peripheral region.SOLUTION: There are provided: the green sheet including a wiring board region 1a and a peripheral region 1b provided around the wiring board region 1a, wherein the hardness of the peripheral region 1b is greater than that of the wiring board region 1a; and a wiring mother board including a wiring board region 1a and a peripheral region 1b provided around the wiring board region 1a, wherein the hardness of the peripheral region 1b is greater than that of the wiring board region 1a.
摘要翻译：要解决的问题：提供一种用于制造布线母板的生片，其中布线板区域的变形由周边区域减小。本发明提供：包括布线板区域1a和周边区域的生片 1b布置在布线板区域1a周围，其中周边区域1b的硬度大于布线板区域1a的硬度; 以及布线母板，其包括设置在布线基板区域1a周围的布线基板区域1a和周边区域1b，其中周边区域1b的硬度大于布线基板区域1a的硬度。

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