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1. 发明专利

JP2004235347A Insulating ceramics and multilayer ceramic substrate using the same 审中-公开
公开(公告)号：JP2004235347A
公开(公告)日：2004-08-19
申请号：JP2003020865
申请日：2003-01-29
申请人： Kyocera Corp , 京セラ株式会社
发明人： TOMISAKO MASAHIRO , KODAMA KAZUYOSHI , NISHIURA TAKASUKE , HAMANO SATOSHI
IPC分类号： H05K3/46 , H01L23/15
摘要： PROBLEM TO BE SOLVED: To provide an insulating ceramics whose specific resistance is 10
11 Ωcm or higher even in the case the thickness is 100 μm or less, and to provide a multilayer ceramic substrate using the same.
SOLUTION: A multilayer ceramic substrate 1 comprises an insulating board 2 where a plurality of insulating layers 2a-2f are laminated, and a wiring circuit layer 3 arranged on the surface of the insulating board 2 and among the insulting layers 2a-2f. At least one layer, or the insulating layer 2a, between the insulating layers 2a and 2f comprises a thin layer of 100 μm or less. The maximum diameter of the crystallite constituting the insulating layers 2a and 2f comprising the thin layer is set to be 5 μm or less, a void area rate to be 3% or less, and maximum void bore to be 5 μm or less, so that the specific resistance of the insulating layer is 10
11 Ωcm or higher, resulting in preventing occurrence of failure at plating.
COPYRIGHT: (C)2004,JPO&NCIPI

2. 发明专利

JP2004063811A Wiring substrate and its manufacturing method 审中-公开
标题翻译：接线基板及其制造方法
公开(公告)号：JP2004063811A
公开(公告)日：2004-02-26
申请号：JP2002220483
申请日：2002-07-29
申请人： Kyocera Corp , 京セラ株式会社
发明人： HAMANO SATOSHI , KIMURA TETSUYA , SHIGEOKA TOSHIAKI , TAMI YASUHIDE
IPC分类号： H05K3/22 , H01L23/13 , H05K3/20 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a wiring substrate in which a wiring circuit layer composed of a metal foil is firmly bonded to the surface of an insulating substrate, and to provide a method for manufacturing the wiring substrate which can form the wiring substrate easily with a high production yield. SOLUTION: The steps comprise a step of manufacturing a ceramic green sheet 1, forming a wiring circuit layer 3 of the metal foil on a surface of a transfer film 4, transferring the wiring circuit layer 3 on the surface of the transfer film 4 to the surface of the green sheet 1, coating a ceramic based insulating paste 5 on the entire formation surface of the wiring circuit layer 3 of the green sheet 1 formed with the wiring circuit layer 3, baking the green sheet 1 coated with the ceramic based insulating paste 5 to manufacture a precursor of the wiring substrate, and grinding a surface side coated with the ceramic based insulating paste 5 in the precursor of the wiring substrate until the wiring circuit layer 3 is exposed. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种布线基板，其中由金属箔构成的布线电路层牢固地结合到绝缘基板的表面，并且提供一种可以形成布线的布线基板的制造方法底物容易生产，产量高。解决方案：步骤包括制造陶瓷生片1的步骤，在转印膜4的表面上形成金属箔的布线电路层3，将布线电路层3转印到转印膜的表面上 4到生片1的表面，在形成有布线电路层3的生片1的布线电路层3的整个形成表面上涂覆陶瓷基绝缘膏5，烘烤涂覆有陶瓷的生片1 制造布线基板的前体，并且在布线基板的前体中研磨在陶瓷基绝缘膏5上涂覆的表面侧，直到布线电路层3露出为止。版权所有（C）2004，JPO

3. 发明专利

JP2003101226A METHOD FOR MANUFACTURING MULTILAYER WIRING BOARD 审中-公开
公开(公告)号：JP2003101226A
公开(公告)日：2003-04-04
申请号：JP2001294747
申请日：2001-09-26
申请人： KYOCERA CORP
发明人： SHIGEOKA TOSHIAKI , KIMURA TETSUYA , HAMANO SATOSHI , TAMI YASUHIDE
IPC分类号： H05K3/46
摘要： PROBLEM TO BE SOLVED: To obtain a multilayer wiring board which has a wiring circuit layer made of a metal foil arranged at least therein, and in which an insulation fault between wiring circuit layers due to the invasion of a moisture does not occur in plating or in a high humidity atmosphere, by generating a gap at the periphery of the internal wiring circuit layer. SOLUTION: A method for manufacturing the multilayer wiring board comprises the steps of coating to form the wring circuit layer 13 made of the metal foil on the surface of a green sheet 11 containing a vitreous component or a mixture of the vitreous component and a ceramic filler component, coating a plasticizer together with an organic binder on the periphery of the layer 13 in a width of 30 μm or more to form a plasticizer-containing layer 14, then laminating the green sheets, and baking the laminate.

4. 发明专利

JPH1125754A MANUFACTURE OF COPPER-METALLIZED COMPOSITION AND GLASS-CERAMIC SUBSTRATE 失效
公开(公告)号：JPH1125754A
公开(公告)日：1999-01-29
申请号：JP17257897
申请日：1997-06-27
申请人： KYOCERA CORP
发明人： SHIGEOKA TOSHIAKI , HAMANO SATOSHI
IPC分类号： H05K1/09 , H01B1/16 , H05K3/12
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a copper-metallized composition which is superior in adhesion to a substrate and of a glass-ceramic substrate by suppressing the occurrence of a warpage of the substrate in the case of simultaneous firing with the glass-ceramic substrate. SOLUTION: In this method, the manufacture of a glass-ceramic substrate is conducted such that copper powder and a metallized paste, which includes glass powder and a vehicle, are printed on the surface of a green sheet, including a raw-material powder composed of a glass-ceramic composition, and that the sheet is fired in a nitrogen atmosphere at a temperature of 800 to 1100 deg.C. In this case, copper powder, which has oxide films on surfaces, an oxygen content in the copper powder of 0.3 to 5.0 pts.wt. relative to 100 pts.wt. of its copper component, and whose average particle diameter is 2 to 6 μm, is used as the copper powder in the metallized paste.

5. 发明专利

JPH08175869A GLASS-CERAMIC SINTERED BODY AND ITS PRODUCTION 失效
公开(公告)号：JPH08175869A
公开(公告)日：1996-07-09
申请号：JP32015294
申请日：1994-12-22
申请人： KYOCERA CORP
发明人： YONEKURA HIDETO , HAMANO SATOSHI
IPC分类号： C04B35/00 , C03C10/00 , C04B35/18 , C04B35/48 , H01L23/15 , H05K1/03 , H05K3/46 , C04B35/495
摘要： PURPOSE: To obtain a glass-ceramic sintered body capable of being baked at 900-1000 deg.C and having high dielectric constant and high strength. CONSTITUTION: This glass-ceramic sintered body comprises 40-70wt.% of Zr in terms of ZrO2 and the rest % of Si, Al, Mg, Zn and B and consists of a crystalline phase comprising zirconia crystalline phase 1, spinel crystalline phase 2 (MgO Al2 O3 , ZnO Al2 O3 ) and a glass phase 3. The glass-ceramic sintered body can be obtained, e.g. by adding a binder to a mixture powder comprising 30-60wt.% of SiO2 -Al2 O3 -MgO-ZnO-B2 O3 based crystalline glass and 40-70wt.% of zirconia, molding into a predetermined shape and baking the molded product in a nonoxidizing atmosphere at 900-1000 deg.C.

6. 发明专利

JPH08148783A CU PASTE AND MULTILAYER PRINTED CIRCUIT BOARD MANUFACTURING METHOD 失效
公开(公告)号：JPH08148783A
公开(公告)日：1996-06-07
申请号：JP29007294
申请日：1994-11-24
申请人： KYOCERA CORP
发明人： HAMANO SATOSHI , ONITANI MASAMITSU , KONAGA TOMOMI , OTOMARU HIDEKAZU
IPC分类号： H05K1/09 , H05K3/46
摘要： PURPOSE: To provide a Cu paste and multilayer printed circuit board manufacturing method wherein it is excellent in planting workability and solder wettability and has a high adhesion strength and its electric resistance can be reduced. CONSTITUTION: A Cu paste is composed of a Cu powder (100vol.%) and amorphous SiO2 -Al2 O3 -B2 O3 -RO (RO: alkali earth metal oxide) glass powder (1-4.5vol.%). Such Cu paste is printed on a green sheet composed of a crystalline SiO2 -Al2 O3 -B2 O3 -MgO-ZnO glass powder, alumina powder and organic component, and the green sheets are laminated and baked in a nitrogen atmosphere.

7. 发明专利

JP2004152903A Method of manufacturing multilayer wiring substrate 审中-公开
公开(公告)号：JP2004152903A
公开(公告)日：2004-05-27
申请号：JP2002314959
申请日：2002-10-29
申请人： Kyocera Corp , 京セラ株式会社
发明人： KIMURA TETSUYA , HAMANO SATOSHI
IPC分类号： C04B41/88 , H01L23/12 , H05K3/20 , H05K3/38 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To eliminate failure when transferring a wiring circuit layer and suppress delamination of the wiring circuit layer even after baking in the process that the wiring circuit layer is formed with the transfer from a transfer sheet to the surface of a ceramic green sheet. SOLUTION: A multilayer wiring substrate can be manufactured by preparing a transfer sheet 4 which is configured by forming the wiring circuit layer consisting of a metal foil on the surface of the transfer sheet 4, transferring and forming the wiring circuit layer 3 to the surface of a ceramic green sheet 1 from the transfer sheet 4, laminating a plurality layers of the green sheet 1, and baking the wiring circuit layer 3 at the temperature lower than the melting point of a metal used to form the wiring circuit layer 3. In this method, after the surface of the wiring circuit layer 3 on the transfer sheet 4 is irradiated with the plasma, a pattern is transferred to the surface of the green sheet 1. COPYRIGHT: (C)2004,JPO

8. 发明专利

JP2003249755A METHOD FOR PRODUCING CERAMIC MULTILAYER PRINTED WIRING BOARD AND CERAMIC MULTILAYER PRINTED WIRING BOARD 审中-公开
公开(公告)号：JP2003249755A
公开(公告)日：2003-09-05
申请号：JP2002047088
申请日：2002-02-22
申请人： KYOCERA CORP
发明人： SHIGEOKA TOSHIAKI , HAMANO SATOSHI , TAMI YASUHIDE , KIMURA TETSUYA
IPC分类号： H05K1/02 , H01L23/12 , H05K3/00 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a method for producing a ceramic multilayer printed wiring board in which occurrence of dimensional shift of a wiring circuit layer due to deformation of a substrate in the vicinity of side end face is prevented at the time of producing a multilayer printed wiring board using a restriction sheet, and a ceramic multilayer printed wiring board having excellent dimensional accuracy. SOLUTION: The method for producing a ceramic multilayer printed wiring board comprises a step for forming a wiring circuit layer 13 in the region of 3 mm or more inside from the circumferential edge part of a ceramic green sheet 11, a step for laying a plurality of green sheets 11 on which the wiring circuit layer 13 is formed in layers, a step for making a cut 14 of 0.01-1 mm in depth in the peripheral part of at least one surface of a multilayer 15 not to traverse the wiring circuit layer 13 in the plan view, a step for laying a ceramic sheet 16 not shrinking at the time of firing in layer on the surface of the multilayer 15 in which the cut 14 is made and then firing it while controlling shrinkage in the planar direction, a step for removing the fired ceramic sheet 16, and a step for cutting and removing at least the peripheral part of the fired multilayer 15 along the cut 14. COPYRIGHT: (C)2003,JPO

9. 发明专利

JP2002353626A MULTILAYER WIRING BOARD AND METHOD OF MANUFACTURING THE SAME 失效
公开(公告)号：JP2002353626A
公开(公告)日：2002-12-06
申请号：JP2001159631
申请日：2001-05-28
申请人： KYOCERA CORP
发明人： SHIGEOKA TOSHIAKI , KIMURA TETSUYA , HAMANO SATOSHI
IPC分类号： H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a multilayer wiring board wherein wiring circuit layers formed of a metal foil are disposed at least inside and which enables to prevent the generation of defective insulation between the wiring circuit layers due to the entrance of moisture in a plating process or in a high moisture environment which is caused by the generation of a space around the internal wiring circuit layers or by the generation of voids due to bad sintering. SOLUTION: The multilayer wiring board comprises an insulation substrate 2 formed by stacking ceramic insulation layers 2a-2d, and the wiring circuit layers 3 formed of a metal foil disposed at least between the insulation layers 2a-2d. In the multilayer wiring board, ceramic layers 6 are formed around the wiring circuit layers formed in the same plane as the wiring circuit layers 3 formed of a metal foil. The ceramic layers 6 have a superior sinterability than the ceramic insulation layers 2a-2d, includes a larger quantity of glass than the ceramic insulation layers 2a-2d, and has a lower glass softening point than that of the ceramic insulation layers 2a-2d.

10. 发明专利

JP2002050865A GLASS-CERAMIC WIRING BOARD AND METHOD OF MANUFACTURING IT 失效
公开(公告)号：JP2002050865A
公开(公告)日：2002-02-15
申请号：JP2000231745
申请日：2000-07-31
申请人： KYOCERA CORP
发明人： TOMISAKO MASAHIRO , HAMANO SATOSHI , SHIGEOKA TOSHIAKI , KODAMA KAZUYOSHI , KIMURA TETSUYA
IPC分类号： H05K3/38 , H01L23/15 , H05K3/20 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a glass-ceramic wiring board provided with fine wiring conductor layers having low resistance and high strength of adhesion. SOLUTION: The glass-ceramic wiring board (multilayered wiring board) 1 which is provided with an insulation substrate 2 composed at least of one glass-ceramic insulation layer 2a-2d, the wiring conductor layers 3 formed on and/or in the substrate 2 and composed of a high-purity metallic conductor containing metallic particles of >=99.5 wt.%, and an adhesive layer 4 which is formed in the interface of at least parts of the wiring conductor layers 3 and the insulation substrate 2 and contains metallic particles scattered in glass is manufactured.

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