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21. 发明专利

JPS6298443A DATA PROCESSOR 失效
公开(公告)号：JPS6298443A
公开(公告)日：1987-05-07
申请号：JP23736285
申请日：1985-10-25
申请人： HITACHI LTD
发明人： KURAKAZU KEIICHI
IPC分类号： G06F15/78 , G06F12/00 , G06F12/02 , G06F12/06
摘要： PURPOSE:To effectively and efficiently use a built-in RAM by providing a route for generating the select signal of the RAM by a micro-instruction, and bringing the built-in RAM to access, based on address information, in addition to a route for bringing the built-in RAM to access by an address. CONSTITUTION:A macro-instruction stored in an external memory is read out by an address signal outputted into an address bus 8 from an address register AR, and supplied to an FIFO 3 through a data bus 9. On a signal chip microcomputer, a built-in RAM 10 which can be used as a general register is provided. Also, in an LSI chip 1, a RAM base register 11 for designating in which position in an address space of the single chip microcomputer the memory space of a built-in RAM 10 exists is provided. The built-in RAM 10 can be relocated in other optional position in the address space, and an address decoder 12 is provided in order to bring the built-in RAM 10 to access.

22. 发明专利

JPS60189047A Data processing device 失效
标题翻译：数据处理设备
公开(公告)号：JPS60189047A
公开(公告)日：1985-09-26
申请号：JP4202484
申请日：1984-03-07
申请人： Hitachi Ltd
发明人： KURAKAZU KEIICHI , KEIDA HARUO
IPC分类号： G06F11/22 , G06F12/16 , G06F13/28 , G06F15/78 , G11C7/00 , G11C29/00 , G11C29/02 , G11C29/56
CPC分类号： G11C29/04 , G11C2029/0401
摘要： PURPOSE:To shorten the testing time of an incorporated RAM by providing a switching circuit through which data can be transferred directly from an input/output port to the RAM or from the RAM to the input/output port. CONSTITUTION:In case of testing of a RAM3, a micro instruction to write data on an internal bus 8 onto an address position indicated by a program counter 4 is sent to a CPU1 from an external test device 10 through an input/output port 6. Then, the micro instruction is read out, and the start address of the RAM3 is set to the counter 4 by a control signal outputted from the CPU1. Simultaneously, a switching circuit 11 is switched to make it possible that data is transferred directly from the input/outut port 6 to the RAM3 through the bus 8, and the RAM3 is set to the write state by a write signal from the CPU1. Thereafter, contents of the counter 4 are counted up or down for every one cycle by the signal from the CPU1, and contents of the RAM3 are outputted to the bus 8 successively.
摘要翻译：目的：通过提供一个开关电路，可以将数据直接从输入/输出端口传输到RAM或从RAM传输到输入/输出端口，从而缩短了内置RAM的测试时间。构成：在测试RAM3的情况下，将内部总线8上的数据写入由程序计数器4指示的地址位置的微指令通过输入/输出端口6从外部测试装置10发送到CPU1。然后，读出微指令，并通过CPU1输出的控制信号将RAM3的开始地址设定为计数器4。同时，切换电路11被切换，使得可以通过总线8将数据直接从输入/输出端口6传送到RAM3，并且通过来自CPU1的写入信号将RAM3设置为写入状态。此后，通过CPU1的信号对计数器4的内容进行每一个周期的上下计数，并将RAM3的内容依次输出到总线8。

23. 发明专利

JP2001067219A CIRCUIT AND METHOD FOR DIVISION 失效
公开(公告)号：JP2001067219A
公开(公告)日：2001-03-16
申请号：JP2000212452
申请日：2000-07-13
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KAWASAKI SHUNPEI , TAWARA YASUHIRO , FUKADA KAORU , YAMAZAKI TAKANAGA , SAKAKIBARA EIJI , KURAKAZU KEIICHI , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KASHIWAGI YUUGO , FUJITA HIDEYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAGI HIDEAKI , SUGAWARA MASAHIKO , UMINAGA MASAHIRO , NOGUCHI YOSHIKI , WATABE MITSURU , TSUKAMOTO TAKU , MASUMURA SHIGEKI
IPC分类号： G06F7/537 , G06F7/52 , G06F7/535 , G06F9/30 , G06F9/34 , G06F9/355 , G06F15/78
摘要： PROBLEM TO BE SOLVED: To prevent the use of immediate data and absolute address specification from being restricted even if the number of bits of a fixed-length instruction format is less than the length of a data word by adopting the fixed-length instruction format whose number of bits is less than maximum data word length. SOLUTION: A microcomputer has RISC type architecture and also has an instruction format of fixed length. A bus where data and instructions are transferred has 32-bit constitution. The instructions, on the other hand, are in 16-bit fixed-length instruction format. This 16-bit fixed-length instruction format is employed for 32-bit data word length and then where an instruction border is present can be decided before a last instruction is completed as well as a RISC machine having a conventional 32-bit fixed-length instruction format since the instruction format has the fixed length. Consequently, such problem that a memory needs to be increased in circuit scale can be evaded.

24. 发明专利

JP2545789B2 失效
公开(公告)号：JP2545789B2
公开(公告)日：1996-10-23
申请号：JP8544286
申请日：1986-04-14
申请人： HITACHI LTD
发明人： WATANABE HIROSHI , KURAKAZU KEIICHI , KASHIWAGI JUGO , TOYAMA KEISUKE , NOJIRI TOORU
IPC分类号： G06F15/00 , G06F9/30 , G06F9/318 , G06F9/355 , G06F9/40 , G06F9/42 , G06F9/46 , G06F9/48 , G06F12/00 , G06F12/02

25. 发明专利

JPH0827716B2 失效
公开(公告)号：JPH0827716B2
公开(公告)日：1996-03-21
申请号：JP23735985
申请日：1985-10-25
申请人： HITACHI LTD
发明人： KURAKAZU KEIICHI , BABA SHIRO
IPC分类号： G06F9/305 , G06F7/00 , G06F9/22 , G06F9/30 , G06F9/318 , G06F9/32

26. 发明专利

JPH03252783A DATA PROCESSOR 失效
公开(公告)号：JPH03252783A
公开(公告)日：1991-11-12
申请号：JP4935390
申请日：1990-03-02
申请人： HITACHI LTD
发明人： YAMAZAKI TAKANAGA , BABA SHIRO , KURAKAZU KEIICHI , ANDO MASAHARU , TANAKA NORIO , KANEKO SUSUMU
IPC分类号： G09G5/00 , G06T11/00 , G09G5/20 , G09G5/24 , G09G5/36
摘要： PURPOSE:To execute a large quantity of computation at high speed by providing a microprocessor, and a digital signal processor including a sequence control part, an execution part, and control storage on which data processing algorithm is described at one semiconductor substrate. CONSTITUTION:A single chip microcomputer 1 comprises integrating a CPU2 as the microprocessor, the digital signal processor (DSP) 3 having a floating point computing function to perform outline font development, a direct memory access controller(DMAC) 6 having a data block transfer function such as bit block transfer, a dual port RAM 4, and a peripheral circuit 7 including a ROM which stores the operating program of the CPU2 and a serial communication interface controller(SCI) which performs data communication between the outside, etc., on one semiconductor substrate. Thereby, it is possible to execute a large quantity of computation at high speed.

27. 发明专利

JPS6412340A DATA PROCESSOR 失效
公开(公告)号：JPS6412340A
公开(公告)日：1989-01-17
申请号：JP16808687
申请日：1987-07-06
申请人： HITACHI LTD
发明人： KURAKAZU KEIICHI , AOTO GIICHI
IPC分类号： G06F9/48 , G06F9/46 , G06F11/22
摘要： PURPOSE:To easily perform the break of a user program including an ordinary interruption processing, by providing another interrupt function other than general interruption, and using a data processor as an emulator. CONSTITUTION:In a case where a microprocessor is used as an incircuit emulator, a signal is supplied to a mode setting terminal MOD. A mode decision circuit decodes the signal, and sets a signal ICE at a high level. According to the above, an AND gate circuit G is opened, and the signal from a break terminal can be inputted. In the development of software using the microprocessor, when the user program advances to an address on which the break is desired to be applied, the fact is detected, and a break terminal BRK is set at the high level. Such break request signal is transmitted to an interruption control circuit via the AND gate circuit G.

28. 发明专利

JPS63136159A DATA PROCESSOR 失效
公开(公告)号：JPS63136159A
公开(公告)日：1988-06-08
申请号：JP28174586
申请日：1986-11-28
申请人： HITACHI LTD
发明人： KANEKO SUSUMU , KURAKAZU KEIICHI , OKUZAKI KOJI , KIDA HIROYUKI
IPC分类号： G06F1/24 , G06F1/00 , G06F12/00 , G06F15/78 , G11C11/34 , G11C11/401 , G11C11/406
摘要： PURPOSE:To avoid destruction of data on a dynamic RAM by initializing only a circuit excluding those circuit that undergo time control in case of resetting other than a power ON resetting. CONSTITUTION:A manual reset signal r2 is produced from three control signals RES, BRTRY and NMI and then supplied to all circuits excluding a refresh controller 2 and bus arbiter 4. In other words, the controller 2 is not initialized in a manual reset mode and at the same time the bus right is delivered to the controller 2 from a CPU1 via the bus arbiter 4. Thus a refreshing action can be continued to an external dynamic RAM. Furthermore this refreshing action is continuous without reloading data after a reset period since a control register, etc., are not initialized within the controller 2.

29. 发明专利

JPS6352241A MICROPROCESSOR 失效
公开(公告)号：JPS6352241A
公开(公告)日：1988-03-05
申请号：JP19530386
申请日：1986-08-22
申请人： HITACHI LTD
发明人： KURAKAZU KEIICHI , OOTA YUJI , KIDA HIROYUKI
IPC分类号： G06F9/42 , G06F9/46 , G06F9/48 , G06F11/00 , G06F15/78
摘要： PURPOSE:To process data at a high speed via a context switching or return action by providing a pointer which designates register groups and a circuit which detects the overflow of the pointer. CONSTITUTION:An MPU contains register groups A-N obtained by dividing the inside area of a RAM and a condition register CR which detects the overflow. These register groups A-N include program counters PCA-N, stack pointers SPA-N, various registers REA-N, and pointers A-N respectively. When an interruption signal is delivered from an interruption circuit INT, the CR gives an indication to an instruction decoder DCR to give accesses to the register groups in the order of A and B-N. When a context switching action occurs in an application mode of the final group N, the CR detects an overflow and produces an interruption signal to deliver the control to a central processing unit.

30. 发明专利

JPS62191931A MICROPROGRAM CONTROL METHOD 失效
公开(公告)号：JPS62191931A
公开(公告)日：1987-08-22
申请号：JP3305586
申请日：1986-02-19
申请人： HITACHI LTD
发明人： KIDA HIROYUKI , MAEJIMA HIDEO , KATSURA AKIHIRO , KURAKAZU KEIICHI
IPC分类号： G06F9/22 , G06F9/26
摘要： PURPOSE:To remarkably reduce the capacity of a microprogram required for executing all microinstructions by permitting plural microinstructions to call the microprogram necessary for executing the microprograms in common as a subroutine. CONSTITUTION:Plural microinstructions call and use the microprogram for executing microinstructions as a subroutine in common. When the microinstruction is stored in an instruction storage part 10, the instruction code of the microinstruction becomes a signal 10a and is inputted to the 1st address generator circuit 11. It outputs a microprogram address obtained by synthesizing the contents of the signal 10a and page information specified by a signal 14b as a signal 11a to a microprogram address register 13. A signal 11b denoting that an effective address lies in the signal 11a becomes active. At that time, the microprogram address register 13 stores the signal 11a as an effective microprogram address, and outputs the contents as a signal 13a to a microprogram memory 14.

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