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1. 发明专利

JPH11102286A CIRCUIT AND METHOD FOR DIVISION 失效
公开(公告)号：JPH11102286A
公开(公告)日：1999-04-13
申请号：JP15814398
申请日：1998-06-05
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KAWASAKI SHUNPEI , TAWARA YASUHIRO , FUKADA KAORU , YAMAZAKI TAKANAGA , SAKAKIBARA EIJI , KURAKAZU KEIICHI , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KASHIWAGI YUUGO , FUJITA HIDEYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAGI HIDEAKI , SUGAWARA MASAHIKO , UMINAGA MASAHIRO , NOGUCHI YOSHIKI , WATABE MITSURU , TSUKAMOTO TAKU , MASUMURA SHIGEKI
IPC分类号： G06F7/537 , G06F7/52 , G06F7/535 , G06F9/30 , G06F9/305 , G06F9/32 , G06F9/38
摘要： PROBLEM TO BE SOLVED: To provide a circuit and a method for division with which a correct quotient can be easily found without detecting whether the partial remainder is '0' or not for each step of division for finding the quotient bit even when a dividend is negative. SOLUTION: When a dividend X is negative in the coded division expressed as Y (quotient) = X (dividend) ÷ 3 (divisor), for example, preprocessing is performed to define a value (X-1) subtracting '1' from the dividend X as a dividend. The preprocessing is processing for conceptionally shifting the coordinate axis of the quotient Y to left for '1'. The processing of division is performed in the shifting state. Thus, it is not necessary to discriminate whether the partial remainder is '0' or not conventionally every time in the middle of arithmetic processing and a hardware for that discrimination is unnecessitated as well. When finding the exact remainder, the found remainder is finally corrected.

2. 发明专利

JPH1196000A CPU AND MICROCOMPUTER 失效
公开(公告)号：JPH1196000A
公开(公告)日：1999-04-09
申请号：JP15814298
申请日：1998-06-05
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KAWASAKI SHUNPEI , TAWARA YASUHIRO , FUKADA KAORU , YAMAZAKI TAKANAGA , SAKAKIBARA EIJI , KURAKAZU KEIICHI , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KASHIWAGI YUUGO , FUJITA HIDEYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAGI HIDEAKI , SUGAWARA MASAHIKO , UMINAGA MASAHIRO , NOGUCHI YOSHIKI , WATABE MITSURU , TSUKAMOTO TAKU , MASUMURA SHIGEKI
IPC分类号： G06F9/30 , G06F9/35
摘要： PROBLEM TO BE SOLVED: To prevent the utilization of immediate data or the designation of an absolute address from being limited even when the number of bits of a fixed length instruction format is less than the data word length, by adopting the fixed length instruction format having bits less than the maximum data word length supplied to an instruction executing means. SOLUTION: IRH and IRL are the instruction buffers of 16 bits respectively, and an instruction is transferred through an internal data bus for the unit of 32 bits while being stored one by one. These instructions are loaded through a multiplexer MPX to an instruction register IR1. The instruction register IR1 has 16 bits. Thus, since the fixed length instruction format of 16 bits is adopted for the data word length of 32 bits, the judgement on where an instruction border exists, can be grasped before the completion of the preceding instruction, and the advantage of the simplification of instruction decode processing or the like is guaranteed. Further, the useless arrangement of bits is decreased and the utilization efficiency of a program memory is improved.

3. 发明专利

JP2000029692A CENTRAL PROCESSOR 失效
公开(公告)号：JP2000029692A
公开(公告)日：2000-01-28
申请号：JP13977299
申请日：1999-05-20
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KAWASAKI SHUNPEI , TAWARA YASUHIRO , FUKADA KAORU , YAMAZAKI TAKANAGA , SAKAKIBARA EIJI , KURAKAZU KEIICHI , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KASHIWAGI YUUGO , FUJITA HIDEYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAGI HIDEAKI , SUGAWARA MASAHIKO , UMINAGA MASAHIRO , NOGUCHI YOSHIKI , WATABE MITSURU , TSUKAMOTO TAKU , MASUMURA SHIGEKI
IPC分类号： G06F9/355 , G06F9/34
摘要： PROBLEM TO BE SOLVED: To decrease program capacity or increase the efficiency of a program memory and to reduce the system cost by adopting a fixed-length instruction format whose bit number is less than the maximum data word length supplied to an instruction executing means. SOLUTION: An instruction register IR1 holds an instruction present at an instruction decoding means. The decoding results of a source register decoder SRD and a destination register decoder DRD are used to specify which of general register R0H, R0L to R15H, and R15L included in an execution part EXEC is selected. With a data transfer instruction, data stored in the address obtained by adding a value of displacement and the value of an address stored in a program counter are transferred to one of registers. In this case, the fixed-length instruction format whose bit number is less than the maximum data word length supplied to the instruction execution means is adopted.

4. 发明专利

JP2001067219A CIRCUIT AND METHOD FOR DIVISION 失效
公开(公告)号：JP2001067219A
公开(公告)日：2001-03-16
申请号：JP2000212452
申请日：2000-07-13
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KAWASAKI SHUNPEI , TAWARA YASUHIRO , FUKADA KAORU , YAMAZAKI TAKANAGA , SAKAKIBARA EIJI , KURAKAZU KEIICHI , AKAO YASUSHI , BABA SHIRO , KIHARA TOSHIMASA , KASHIWAGI YUUGO , FUJITA HIDEYA , ISHIDA KATSUHIKO , SAWA NORIKO , ASANO YOICHI , CHAGI HIDEAKI , SUGAWARA MASAHIKO , UMINAGA MASAHIRO , NOGUCHI YOSHIKI , WATABE MITSURU , TSUKAMOTO TAKU , MASUMURA SHIGEKI
IPC分类号： G06F7/537 , G06F7/52 , G06F7/535 , G06F9/30 , G06F9/34 , G06F9/355 , G06F15/78
摘要： PROBLEM TO BE SOLVED: To prevent the use of immediate data and absolute address specification from being restricted even if the number of bits of a fixed-length instruction format is less than the length of a data word by adopting the fixed-length instruction format whose number of bits is less than maximum data word length. SOLUTION: A microcomputer has RISC type architecture and also has an instruction format of fixed length. A bus where data and instructions are transferred has 32-bit constitution. The instructions, on the other hand, are in 16-bit fixed-length instruction format. This 16-bit fixed-length instruction format is employed for 32-bit data word length and then where an instruction border is present can be decided before a last instruction is completed as well as a RISC machine having a conventional 32-bit fixed-length instruction format since the instruction format has the fixed length. Consequently, such problem that a memory needs to be increased in circuit scale can be evaded.

5. 发明专利

JP2002138852A GAS TURBINE FACILITIES 审中-公开
公开(公告)号：JP2002138852A
公开(公告)日：2002-05-17
申请号：JP2001338851
申请日：2001-11-05
申请人： HITACHI LTD
发明人： HATAMIYA SHIGEO , YAMAGISHI MASAHIKO , YOKOMIZO OSAMU , NOGUCHI YOSHIKI , TSUKAMOTO MORIAKI
IPC分类号： F01D25/32 , F02C3/30 , F02C7/08
摘要： PROBLEM TO BE SOLVED: To provide gas turbine facilities for achieving high output and high efficiency while requiring a less change in design of a gas turbine and a less amount of water to be supplied. SOLUTION: A fine droplet spray device 11 is installed in an intake chamber 22 in the upstream of an air compressor 2 and a humidifier 7 is installed therein for humidifying a high pressure air delivered from the compressor 2. In addition, a regenerator 5 is provided for heating the air humidified using a gas turbine exhaust gas as a heat source. Thus, the effect of reducing the power of the compressor 2 and the effect of increasing the output due to the humidification of a combustion air 20 are produced and the amount of a fuel to be used is reduced by adopting a regeneration cycle, improving power generation efficiency.

6. 发明专利

JP2000213371A GAS TURBINE GENERATING METHOD AND GENERATING APPARATUS 失效
公开(公告)号：JP2000213371A
公开(公告)日：2000-08-02
申请号：JP1521899
申请日：1999-01-25
申请人： HITACHI LTD
发明人： KISO FUMIHIKO , HATAMIYA SHIGEO , KOMURO TAKEO , FUKUHARA HIROSHI , AKIYAMA TORU , MORIHARA ATSUSHI , NOGUCHI YOSHIKI
IPC分类号： F02C3/28 , F02C3/30 , F02C7/08
摘要： PROBLEM TO BE SOLVED: To introduce gasified gas in a high temperature, by introducing the gasified gas containing sulfur into a combustor and then making exhaust gas which is discharged from a gas turbine contact with water containing deslfurizing agent to separate and recover sulfur from the exhaust gas. SOLUTION: Coal gasification gas from which ash and ammonia are eliminated is introduced into a gas turbine combustor 310. In the gas turbine combustor 310, the coal gasification gas is brunt by humidification compressed air 24. Hydrogen sulfide and carbonyl sulfide contained in the coal gasification gas is turned into sulfur dioxide by the gas turbine combustor 310. The gas generated by the gas turbine combustor 310 is used as working medium gas 15 for a gas turbine 330 which is driven to obtain electric power generated in a ganerator 340. The gas turbine 330 exhausts gas turbine exhaust gas 16 containing the sulfur dioxide and moisture. The gas turbine exhaust gas 16 is separated and recovered by a water recovery/desulfurization device 430. Accordingly, high efficiency is implemented without lowering gasified gas to ordinary temperature.

7. 发明专利

JP2000082038A INFORMATION PROCESSOR 失效
公开(公告)号：JP2000082038A
公开(公告)日：2000-03-21
申请号：JP25071098
申请日：1998-09-04
申请人： HITACHI LTD
发明人： KONDO NOBUKAZU , KAWASAKI IKUYA , NOGUCHI YOSHIKI
IPC分类号： G06F13/42 , G06F13/40
摘要： PROBLEM TO BE SOLVED: To improve both reliability and data efficiency of a source clock synchronous system bus by using a source clock signal exclusive for an acknowledge signal to transmit even the acknowledge signal in a source clock synchronous system. SOLUTION: For instance, a signal line of a system bus of an information processor consists of a source clock signal line 203, nine multiplexed command/ address/data lines 204, an acknowledge signal line 205 and a last cycle signal line 206 with which a bus master previously announces disuse of its bus right. Then this processor transmits even the acknowledge signal in a source clock synchronous system and accordingly a source clock exclusive for the acknowledge signal is added to a bus signal line. Furthermore, an acknowledge signal is used for every basic transfer block of a large number of cycles not for every cycle so that the connection is possible despite mixture of modules of different operating frequencies.

8. 发明专利

JP2000010780A MICROPROCESSOR 失效
公开(公告)号：JP2000010780A
公开(公告)日：2000-01-14
申请号：JP17123498
申请日：1998-06-18
申请人： HITACHI LTD
发明人： KIUCHI ATSUSHI , KAMIMAKI HARUO , NOGUCHI YOSHIKI
IPC分类号： G06F9/38 , G06F17/10 , G06T1/20
摘要： PROBLEM TO BE SOLVED: To provide a microprocessor which can avoid the occurrence of overhead between the load of source data and product-sum operation (or multiplying operation) each time of repeatedly executing multiplication or product-sum operation processing. SOLUTION: In the microprocessor provided with pipeline structure consisting of five stages called IF, ID, EX, MA and WB, product-sum operation or multiplying operation is started at an MA stage. Otherwise, all the operation from the start of operation to the write back of an operating result is completed at the WB stage. Thus, an overhead cycle between data operating operation such as product-sum operating processing and reading out operation of source data required for it can be eliminated.

9. 发明专利

JPH11294187A BIOMASS GASIFYING POWER GENERATION PLANT 失效
公开(公告)号：JPH11294187A
公开(公告)日：1999-10-26
申请号：JP9716698
申请日：1998-04-09
申请人： HITACHI LTD
发明人： KISO FUMIHIKO , MORIHARA ATSUSHI , KOYAMA SHUNTARO , NOGUCHI YOSHIKI
IPC分类号： F02C3/28 , F02C6/18
摘要： PROBLEM TO BE SOLVED: To improve power generation efficiency in a power generation plant adapted to gasify biomass and drive a gas turbine by the gas to generate electric power by transporting the biomass to a drier with air, and supplying some of transported air containing moisture separated from the biomass to a compressor. SOLUTION: Biomass 1 is supplied from a rock hopper 11 to a gasifying furnace 10. In this case, air 2 pressurized by a compressor is used for transporting the biomass 1. Since fine grains are contained in the generated gas 3 obtained by gasifying the biomass 1, the fine grains are removed by a cyclone 20 and a dust removal filter 30. A sulfur compound in the generated gas 3 is removed by a desulfurizing device 40. Further, purified gas 4 is supplied to a gas turbine combuster 52, and burnt by the air 6 supplied from a biomass drier 70 and compressed by the compressor 50. The combustion gas is supplied to the turbine 51 to rotate a power generator 53, thereby obtaining electric output.

10. 发明专利

JPH11232214A PROCESSOR FOR INFORMATION PROCESSOR AND ITS CONTROLLING METHOD 失效
公开(公告)号：JPH11232214A
公开(公告)日：1999-08-27
申请号：JP3454198
申请日：1998-02-17
申请人： HITACHI LTD
发明人： KONDO NOBUKAZU , KOHIYAMA TOMOHISA , NOGUCHI YOSHIKI
IPC分类号： G06F13/28 , G06F13/36 , G06F13/42
摘要： PROBLEM TO BE SOLVED: To improve the efficiency of data on a bus in a system using an address/data multiplexed bus. SOLUTION: A processor for an information processor having a unit 50 for executing arithmetic processing in its inside is provided with buffers 31, 32 capable of storing plural sets of write addresses and data for a system bus 800, a comparator 37 for judging whether the write addresses of mutually continued access requests out of plural access requests stored in the buffer 31 are continued addresses or not and a means 45 for converting plural writing operations for the continued addresses into a burst transfer protocol allowed to be transferred by continuous data cycles continued to one address cycle in the case of detecting the continued write addresses based on the judged result of the comparator 37.

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