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1. 发明专利

JPH10247150A DATA PROCESSING SYSTEM 失效
公开(公告)号：JPH10247150A
公开(公告)日：1998-09-14
申请号：JP5018097
申请日：1997-03-05
申请人： HITACHI LTD , HITACHI CHIYOU LSI SYS KK
发明人： HONGO TORU , AOTO GIICHI
IPC分类号： G06F11/22 , G06F12/02 , G06F17/50
摘要： PROBLEM TO BE SOLVED: To provide a data processing system which can map plural devices variably to the same area. SOLUTION: First information CS6- to- CS0, SW2 to SW0 and A21 to A19 that optionally select the areas obtained by fractionizing further respective areas of plural areas and 2nd information RB7 to RB0 that indicate whether or not the areas designated with the 1st information are used in every areas are inputted, when access to an area whose use is indicated with the 2nd information is detected based on the 1st information, a 1st logic means 30B makes a chip choice of a 1st storage means 31 and when the 1st logic means detects access to the unused area based on the 1st information, a 2nd logic means 30A selects the operation of a 2nd storage means 32.

2. 发明专利

JPH08202580A EMULATOR 失效
公开(公告)号：JPH08202580A
公开(公告)日：1996-08-09
申请号：JP876495
申请日：1995-01-24
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： KOYAMA HIDEAKI , AOTO GIICHI , SASAKI HIROYUKI
IPC分类号： G06F11/28 , G06F11/22
摘要： PURPOSE: To execute emulation in the application system of a multi-CPU system by using one emulator. CONSTITUTION: The emulator which executes the emulation in the application system of a 2-CPU system and is divided into an emulator unit not to be concerned with making into AS such as a part to support the CPU core of a microcomputer, etc., and a target probe 3b to vary in accordance with the making into AS such as the artificial circuit of a peripheral function, etc., is provided with a slave microcomputer 4 to execute substitutionally the function of the target microcomputer of one side between two microcomputers and the slave microcomputer 5 to execute substitionally the funciton of the target microcomputer 5 of the other side. Since the target probe 3b is provided with these slave microcomputers 4, 5, the emulation of the two-CPU system can be executed by using one emulator.

3. 发明专利

JPH0830483A EMULATOR 失效
公开(公告)号：JPH0830483A
公开(公告)日：1996-02-02
申请号：JP16496694
申请日：1994-07-18
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： NAITO YOSHIRO , SUZUKI TATSUYA , AOTO GIICHI
IPC分类号： G06F11/28 , G06F11/22 , G06F15/78
摘要： PURPOSE:To debug a program by making a user optionally alter the timing chart of the execution contents of the program. CONSTITUTION:The user program is traced and an optional signal of the timing chart displayed on a display 2e is altered on a keyboard 2a or with a mouse 2b. The altered timing chart is inputted to a work memory 8 from an I/O 2d through a master bus 10, the user program before the alteration which is executed and the altered user program are converted and transferred to an emulation control circuit 7, and the user program stored in a user memory 1a is erased; and the altered user program is outputted from a user interface 12 to rewrite and store the data in the user memory 1a, and the user alters the pattern of the user program and debugs the program.

4. 发明专利

JPH07281924A TRACE DEVICE AND EMULATOR USING THE TRACE DEVICE 失效
公开(公告)号：JPH07281924A
公开(公告)日：1995-10-27
申请号：JP9294894
申请日：1994-04-05
申请人： HITACHI LTD
发明人： MASUDA SATOSHI , AOTO GIICHI
IPC分类号： G06F11/28
摘要： PURPOSE:To provide a trace device which can acquire the bus information in a data access state, the bus information on the program fetch set right before the data access state, and the bus information on the program fetch set right before/after an instruction execution flow is changed. CONSTITUTION:Each of latch circuits 110 and 111 latches the bus information in each instruction fetch cycle and holds the bus information on two bus cycles when the latch operation is exclusively controlled. The exclusive latch operation is started in response to a state where the instruction execution flow detected by a branch signal 205 is changed and also to a data access state which is detected by a program fetch signal 206. Then the bus information latched after the end of the exclusive latch operation are written in a trace memory 100 in parallel to each other.

5. 发明专利

JP2001267361A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001267361A
公开(公告)日：2001-09-28
申请号：JP2000076339
申请日：2000-03-14
申请人： HITACHI LTD
发明人： UJII TOMOYOSHI , AOTO GIICHI
IPC分类号： H01L21/66 , G06F11/22 , H01L21/60
摘要： PROBLEM TO BE SOLVED: To reduce the number of terminals for external connection. SOLUTION: A film-like board extended part (13) is formed on a film-like board so as to extend from a semiconductor deviceconducted with a terminal for externally connecting, and electrodes(132) capable of communicating a signal with the chip via thepattern are provided on the film-like board extended part. Thus,since the signal not transmitted to the terminal can be fetched, itis not necessary to use the terminal to fetch such a signal. Thisenables reduction in the number of the terminals.

6. 发明专利

JPH11143732A MICROCOMPUTER AND EMULATOR 失效
公开(公告)号：JPH11143732A
公开(公告)日：1999-05-28
申请号：JP30386497
申请日：1997-11-06
申请人： HITACHI LTD
发明人： FUJITA HIDEYA , AOTO GIICHI , NARITA SUSUMU , NISHII OSAMU , SUZUKI TAKASHI
IPC分类号： G06F11/28 , G06F9/46 , G06F9/48 , G06F11/22
摘要： PROBLEM TO BE SOLVED: To improve the efficiency of debugging. SOLUTION: This device is provided with a first means 321 for generating identification information for identifying the destination of restoration after the interrupting processing according to whether interruption is generated in a user mode or a debug mode, and second means 322 for determining the destination of restoration after the end of the interruption processing based on the identification information. Thus, the proper destination of restoration can be determined based on the identification information Thus, it is possible to attain the acceptation of the interruption in the debug mode, and to achieve the improvement of the efficiency of debugging.

7. 发明专利

JPH1173344A EMULATOR 失效
公开(公告)号：JPH1173344A
公开(公告)日：1999-03-16
申请号：JP23467797
申请日：1997-08-29
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： ONDA HIDEO , ITO ATSUYOSHI , AOTO GIICHI
IPC分类号： G06F11/28 , G06F11/22
摘要： PROBLEM TO BE SOLVED: To improve the availability of a trace memory. SOLUTION: This emulator is provided with a status forming means 20A for forming a 1st status signal indicating a repeating period of execution of a loop instruction and a 2nd status signal showing each repeated execution of the loop instruction and trace controlling means 50, 60 for inhibiting tracing in a trace memory 70 during a period from a 1st loop end up to a final loop end based on the 1st and 2nd status signals. Since tracing in the trace memory 70 is inhibited from the 1st loop end up to the final loop end, the repeated writing of arithmetic processing execution results in the memory 70 by the loop instruction can be evaded and the using efficiency of the memory 70 can be improved.

8. 发明专利

JPH08194658A MICROCOMPUTER SYSTEM 失效
公开(公告)号：JPH08194658A
公开(公告)日：1996-07-30
申请号：JP519795
申请日：1995-01-17
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： NOGUCHI HIROKATSU , KOYAMA HIDEAKI , AOTO GIICHI
IPC分类号： G06F13/10
摘要： PURPOSE: To reduce burden for developing a software by unnecessitating the development of the software for initializing the built-in memory interface or the like of a microprocessor. CONSTITUTION: A microprocessor 1 incorporates the memory interface, initializing program for that interface, and control register 10 for storing initializing information and on the other hand, a memory 2 incorporates a register 20 for initialization where its own specification information is stored. Just after the power source of the system is turned on or reset, the microprocessor 1 reads the specification information out of the memory 2 and after the memory interface initialization is performed based on that read specification information, ordinary arithmetic processing or the like is started. Thus, since the initialization for the built-in memory interface or the like in the microprocessor 1 is automatically performed, it is not necessary to prepare software for initializing the interface and burden for software development is reduced.

9. 发明专利

JPH07287663A POWER VOLTAGE MONITOR SYSTEM 失效
公开(公告)号：JPH07287663A
公开(公告)日：1995-10-31
申请号：JP10176194
申请日：1994-04-18
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： SUZUKI TATSUYA , NAITO YOSHIRO , AOTO GIICHI
IPC分类号： G06F1/28 , G06F11/22
摘要： PURPOSE:To provide a power voltage monitor system which can easily decide the basic potential of the power voltage and also can selectively switch the identified potentials for the abnormal drop of the power voltage in response to the basic potential and then to improve the functional performance of an emulator including a user power abnormality detecting part, etc. CONSTITUTION:A user power abnormality detecting part UVCM includes a potential deciding circuit which decides the basic potential of the user power voltage UVCC based on the frequency of the clock signal CLK of a microprocessor. Then the voltage comparators VCP1 and VCP2 are provided together with the AND gates AG1 AG2 and an OR gate OG1. Thus the abnormal drop of the voltage UVCC is identified and a user power voltage abnormality detection signal UVCE and a decode inhibition signal DECI are produced. In such a constitution of an abnormal voltage detection circuit, the identified potentials can be selectively switched based on the deciding result of the basic potential.

10. 发明专利

JPH05233351A 失效
公开(公告)号：JPH05233351A
公开(公告)日：1993-09-10
申请号：JP7346692
申请日：1992-02-25
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： KOYAMA HIDEAKI , ONDA HIDEO , AOTO GIICHI
IPC分类号： G06F11/22 , G06F11/28 , G06F13/28
摘要： PURPOSE:To perform the debug of software even when the usage of memory included in a user system is disabled by a bus master other than the microcomputer of the user system. CONSTITUTION:The debug of the software can be performed when the usage of memory 28 included in an user system 17 is disabled by forming an access route to permit access from another bus master of the user system 17 to circulation memory 8 including a bus buffer 20, and permitting the access to the memory 8 when another bus master 27 other than the microcomputer that should be mounted originally on the user system 17 acquires a bus right.

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