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21. 发明专利

JPH02177436A THERMAL TREATMENT FURNACE 失效
公开(公告)号：JPH02177436A
公开(公告)日：1990-07-10
申请号：JP33237088
申请日：1988-12-28
申请人： FUJITSU LTD , FUJITSU VLSI LTD
发明人： KOBAYASHI MASANORI , NAKAJIMA KAZUJI
IPC分类号： H01L21/31
摘要： PURPOSE:To reduce the cost for replacing a core tube in a shower-type thermal treatment furnace which facilitates uniform and high speed diffusion of reactive gas by a method wherein a gas introducing and spouting part in which a reactive gas introducing inlet and a plurality of gas spouting outlets are provided and the core tube which is coupled with the gas introducing and spouting part so as to be separated freely are provided. CONSTITUTION:A gas introducing and spouting part 2 in which a reactive gas introducing inlet 21 and a plurality of gas spouting outlets 22a through which the reactive gas is diffused and spouted out into a core tube 1 which is coupled with the gas introducing and spouting part 2 so as to be separated freely are provided. For instance, the core tube 1 is a slender cylinder made of quartz material and the surface of the inner wall 11 of its end to which the gas introducing and spouting part 2 is fitted is roughed to form a friction surface. The gas introducing and spouting part 2 is made of quartz or the like and has an approximate funnel-shape and has the reactive gas introducing inlet 21 on one end and a partition plate 22 in which a plurality of the gas spouting outlets 22a are distributed uniformly over the whole surface on the other end and the surface 23 of the fitting part is roughed so as to be coupled with the core tube 1 by a friction method.

22. 发明专利

JPH01305561A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH01305561A
公开(公告)日：1989-12-08
申请号：JP13544388
申请日：1988-06-03
申请人： FUJITSU LTD
发明人： KASOKU HIROMICHI , NIWAYAMA NOBUO , KOBAYASHI MASANORI , MORI HARUHISA , IGARASHI TAKASHI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To reduce occupied area by utilizing capacity at pn junction created by a one conductivity type buried layer and an opposite conductivity type buried layer as a memory capacitor, and connecting it to the impurity diffusion region of a MIS field-effect Tr. CONSTITUTION:An n buried layer 7 is formed to a p type buried layer 2 on a p-type silicon semiconductor substrate 1, and junction capacitance created between them is utilized as a memory capacitor. The layer 7 is connected to the n drain region 12 of a transfer gate Tr through an n type connection region 14. The width of the layer 7 can be made almost equal to or more than the drain region, and the width of the layer 2 of made almost equal to the layer 7 or over the whole face inside a wafer. The capacity in the memory capacitor of DRAM can be easily changed over a fair range, depending upon the impurity concentration of the layer 2 and the layer 7 or by selecting the length or width of the layer 7 leading to the drain region.

23. 发明专利

JPH01154530A WET PROCESSING EQUIPMENT FOR SEMICONDUCTOR SUBSTRATE 失效
公开(公告)号：JPH01154530A
公开(公告)日：1989-06-16
申请号：JP31208387
申请日：1987-12-11
申请人： FUJITSU LTD
发明人： KOBAYASHI MASANORI
IPC分类号： H01L21/304 , H01L21/306 , H01L21/673 , H01L21/68
摘要： PURPOSE:To prevent particles, produced by scribing at the contact part between a hanger and a retaining means, from attaching to a semiconductor substrate mirror surface, by making up a constitution wherein a retaining means to suspend a semiconductor substrate retaining member is positioned above the upper end of a semiconductor substrate. CONSTITUTION:A semiconductor substrate retaining member 3 is composed of the following; at least three rod type member 1 which are mutually arranged and have recessed parts 11 to retain a semiconductor substrate, and end-portion retaining members 2. A wet processing equipment for semiconductor substrate is provided with a retaining means 4 to suspend the semiconductor substrate retaining means 2. In the end-portion retaining member 2, the retaining means 4 are installed at least above the upper end of a semiconductor substrate, thereby eliminating possibility that a contacting part between a hanger H and the semiconductor substrate retaining member 3 is dipped in liquid, and generated particles float on the liquid surface. Even if the contacting part is dipped in the liquid, and the particles float on the liquid surface, a semiconductor substrate W is completely dipped in the chemical liquid, before the contacting part reaches the liquid surface, so that particles never attach to the semiconductor substrate.

24. 发明专利

JPH0198959A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0198959A
公开(公告)日：1989-04-17
申请号：JP25627587
申请日：1987-10-13
申请人： FUJITSU LTD
发明人： KOBAYASHI MASANORI , OGAWA TSUTOMU , MORI HARUHISA , KASE MASATAKA
IPC分类号： H04R17/00 , G01N29/00 , G01N29/28
摘要： PURPOSE:To obtain a measuring means for a sound wave in crystal whose incidence surface is held parallel to the sound wave generation surface of a piezoelectric element by adhering the piezoelectric element and crystal by using a metal and thus constituting the semiconductor device. CONSTITUTION:For example, aluminum 17 is vapor-deposited on the specularly-finished incidence surface of the crystal 11 and the specularly-finished sound wave generation surface of the piezoelectric element 12. Then the piezoelectric element 12 is placed on the crystal 11 and the aluminum is melted at high temperature to adhere the piezoelectric element 12 to the crystal 11. Then even if a room temperature atmosphere changes into a low temperature atmosphere, the aluminum does not change in its solidification state at all and the incidence surface of the crystal 11 and the sound wave generation surface of the piezoelectric element 12 are finished specularly, so the piezoelectric element 12 and crystal 11 are held pressed against each other in parallel. Consequently, the arrival time difference of a sound wave generated owing to the difference in the distance between the sound wave generation surface of the piezoelectric element 12 and the incidence surface of the crystal 11 is eliminated, so the measurement accuracy is improved. Further, the level attenuation of a reflected wave is suppressed, so the detection efficiency is improved.

25. 发明专利

JPS6474744A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6474744A
公开(公告)日：1989-03-20
申请号：JP23300387
申请日：1987-09-17
申请人： FUJITSU LTD
发明人： HASEGAWA HITOSHI , KOBAYASHI MASANORI , KASE MASATAKA
IPC分类号： H01L21/60
摘要： PURPOSE:To equalize the growth rate of a plating and to form a bump of an even film thickness by a method wherein a plating object region is divided into at least two regions of the central part of a semiconductor wafer and the outer peripheral part of the wafer through a scribing line and the plating is controlled on every region. CONSTITUTION:A barrier metallic film 22 on a semiconductor wafer 2 is removed along a scribing line 22c to pass on the peripheral edge end of a range reduced 1/2r from its radius (r) and plating object regions A and B, each consisting of each of barrier metallic films 22a and 22b, are formed. Then, the wafer 21 is set on a jet system plating device, a gold plating solution is blown up through a solution jet part 26 while a prescribed temperature is maintained and a plating is grown on a bump contact window part. Moreover, a plating current is controlled through plating control circuits 23 and 24 for the regions A and B. Thereby, even though a difference is generated between the amount of the plating solution to reach the central part of the plating object region of the wafer 2 and the amount of the plating solution, which is diffused on the outer peripheral part of the wafer and reaches the central part, the growth rate of the plating can be equalized.

26. 发明专利

JPS6414914A JIG FOR MANUFACTURE OF SEMICONDUCTOR 失效
公开(公告)号：JPS6414914A
公开(公告)日：1989-01-19
申请号：JP17079187
申请日：1987-07-08
申请人： FUJITSU LTD , IBIDEN CO LTD
发明人： KOBAYASHI MASANORI , OGAWA TSUTOMU , WADA KUNIHIKO , YOKOYAMA TAKAO
IPC分类号： H01L21/673 , C04B41/88 , C30B35/00 , H01L21/22 , H01L21/68
摘要： PURPOSE:To provide excellent thermal conductivity and to improve thermal unlformity and responsiveness by forming a coating layer made of silicon on a silicon carblde surface and effectively ntilizing the property of silicon. CONSTITUTION:A silicon carbide member 11 for forming a jig 10 for manufacture of semiconductor is composed of a composlte material made of silicon carbide and silicon in such a manner that the member 11 mainly contains the silicon carbide. when it has 3-dimensional matrix structure, a 3-dimenslonal matrix-like skeleton is formed of silicon carbide crystal having loym or less of mean grain size in such a manner that the mean grain size of the crystal is preferably 5mum or less and 30wt.% or more a beta-type crystal silicon carbide is preferably contained. A coating layer to be formed on the member 11 is composed of silicon, and its thickness is preferably 1-100mum.

27. 发明专利

JPS63153813A CONSERVATION OF SEMICONDUCTOR SUBSTRATE 失效
公开(公告)号：JPS63153813A
公开(公告)日：1988-06-27
申请号：JP30211886
申请日：1986-12-17
申请人： FUJITSU LTD
发明人： KOBAYASHI MASANORI
IPC分类号： H01L21/02 , B08B7/00 , B65B55/22 , H01L21/00 , H01L21/304 , H01L21/306 , H01L21/677
摘要： PURPOSE:To prevent the growth of a natural oxidation film and the adhesion, etc., of a contaminant by covering a semiconductor substrate with a film of ice, by freezing pure water while the semiconductor substrate is kept in the pure water and conserving the semiconductor substrate covered with the film of ice at a low temperature at which ice is not melted. CONSTITUTION:Semiconductor substrates 3 erected and arranged onto a washing jig 9 consisting of Teflon, etc., and washed by chemicals and washed preparatorily by water are inserted into a water-washing vessel 12 having a pure-water inflow port 10 and a pure-water discharge port 11 and composed of Teflon, etc., as the substrates are left as they are loaded onto the washing jig 9, and the semiconductor substrates 3 are washed by pure water for a fixed time under the state in which pure water 5 at a predetermined flow rate is flowed in from the pure-water inflow port 10 and discharged from the pure-water discharge port 11. The inflow of pure water 4 is stopped, and pure water 5 filled into a water-washing vessel 12 and covering the semiconductor substrates 3 is frozen in a refrigeration unit 6. The semiconductor substrates 3 are conserved for a prolonged term in a refrigerator 7 kept at approximately -10 deg.C. On usage, the washing vessel 12 is dipped into a water washing tank 8 into which pure water is flowed, and ice 105 in the washing vessel 12 is melted. The semiconductor substrates 3 are extracted together with the washing jig 9, and dried in N2, etc.

28. 发明专利

JPS62166567A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62166567A
公开(公告)日：1987-07-23
申请号：JP951486
申请日：1986-01-20
申请人： FUJITSU LTD
发明人： SASAKI NOBUO , KOBAYASHI MASANORI
IPC分类号： H01L29/78 , H01L21/316 , H01L21/336 , H01L29/786
摘要： PURPOSE:To reduce the irregularity of a Vth even in an SOI in which crystal grain boundaries exist by performing the gate oxidation of an MOSFET at 1,100 deg.C or lower by an HCl oxidizing method to form oxide films of substantially the same thickness even for silicon layers of different azimuths. CONSTITUTION:The gate oxidation of an MOSFET is executed at 1,100 deg.C or lower by an HCl oxidizing method. In other words, oxidizing temperatures are altered to oxidize silicon wafers of planar azimuths (100) and (111). An abscissa axis of a graph indicates the oxidizing temperature, and an ordinate axis indicates the difference of the thicknesses between the oxide film of the (111) plane standardized from the oxide film thickness of (100) plane and the oxide film of the (100) plane. The difference is 45% in case of wet oxidizing method at 900 deg.C, but the difference is reduced to approx. 33% in case of the HCl oxidizing method, and when the oxidizing temperature is further raised, the thickness gradually decreases, and the thickness is reduced at 1,150 deg.C to 5%.

29. 发明专利

JPS6188546A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS6188546A
公开(公告)日：1986-05-06
申请号：JP20923584
申请日：1984-10-05
申请人： Fujitsu Ltd
发明人： KOBAYASHI MASANORI , WADA KUNIHIKO
IPC分类号： H01L25/18 , H01L25/065 , H01L25/07 , H01L29/06 , H01L25/04
CPC分类号： H01L25/0657 , H01L29/0657 , H01L2224/48091 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014
摘要： PURPOSE:To relax the limitation of a connection, and to improve area efficiency by boring a through-hole to a semiconductor chip positioned at an upper section, flowing solder into the through-hole and mutually connecting two semiconductor chips each having circuits and the pads through insulating films on surface layer sections when the chips are superposed and chip-on-chip structure is formed. CONSTITUTION:An insulating film 1c is applied onto the surface of a semiconductor substrate 16 to which a circuit is formed, a connecting pad 3a is shaped onto the film 1c, and the pad 3a is surrounded by an insulating film 1d while being connected to the predetermined section of the circuit, thus forming a first semiconductor chip 1a. A second semiconductor chip 2a stacked onto the chip 1a is also constituted by a connecting pad 4a through a semiconductor substrate 2b and an insulating film 2c, but an opening 4b penetrating the pad 4a and a through-hole 6 penetrating the substrate 2b are bored to the chip 2a when the chips 1a and 2a are superposed. A lower hole 6a is also bored to the film 1d exposed into the hole 6, the side wall of the hole 6 is coated with an insulating film 6b, solder 5a is flowed into the hole 6, and the two pads 6 and 4a are connected with each other.
摘要翻译：目的：为了放松连接的限制，通过将通孔钻孔到位于上部的半导体芯片来提高面积效率，将焊料流入通孔并将两个具有电路和焊盘的两个半导体芯片相互连接当芯片叠置并且形成片上芯片结构时，通过表面层部分上的绝缘膜。构成：在形成有电路的半导体基板16的表面上施加绝缘膜1c，将连接焊盘3a成形为膜1c，并且焊盘3a被绝缘膜1d包围，同时连接到从而形成第一半导体芯片1a。层叠在芯片1a上的第二半导体芯片2a也由通过半导体基板2b和绝缘膜2c的连接焊盘4a构成，但是穿透焊盘4a的开口4b和穿透基板2b的通孔6被钻孔到当芯片1a和2a重叠时的芯片2a。下部孔6a也露出到孔6中的薄膜1d上，孔6的侧壁涂覆有绝缘膜6b，焊料5a流入孔6，并且两个焊盘6和4a连接与彼此。

30. 发明专利

JPS60254620A DRYING METHOD AND APPARATUS OF WAFER 失效
公开(公告)号：JPS60254620A
公开(公告)日：1985-12-16
申请号：JP10947584
申请日：1984-05-31
申请人： FUJITSU LTD
发明人： KOBAYASHI MASANORI , WADA KUNIHIKO , HASEGAWA HITOSHI
IPC分类号： H01L21/304 , H01L21/00
摘要： PURPOSE:To dry perfectly wafers without leaving washing liquid at contacting portions between wafers and the basket, by drying the wafers while blowing gas over the contacting portions between the wafers and the basket in a drying furnace. CONSTITUTION:A drying apparatus has a drying furnace 2 whose inside have been previously heated by a heater 2a and in which a gas blowing member 4 is installed. A gas supplying pipe 5 is connected to the gas blowing member 4 from which gas G is always being blowed. After washing, wafers 1 putted in a basket 3, are inserted into the drying furnace and are set over the blowing member 4. Since the evaporation effect of the washing liquid being left at the contacting portions between the wafers 1 and the basket 3 can be increased by the gas blowing, the wafers 1 can be dried perfectly.

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