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11. 发明专利

JPH07161988A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH07161988A
公开(公告)日：1995-06-23
申请号：JP30772993
申请日：1993-12-08
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SHIMIZU AKIHIRO , OYU SHIZUNORI , OOKI NAGATOSHI , ISHIDA HIROSHI , YAMANAKA TOSHIAKI , HASHIMOTO KOJI
IPC分类号： H01L29/43 , H01L21/265 , H01L21/336 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/786
摘要： PURPOSE:To provide a manufacturing method by which thin junction source and drain of a MIS type field-effect transistor are effectively formed and gate insulation breakdown strength is not deteriorated. CONSTITUTION:A manufacturing method includes a step of introducing impurities for forming source and drain regions 5 after a gate electrode 3 is patterned; and a step of forming a thin film insulation film at a high temperature for a short time by a rapid heating and cooling method and simultaneously activating initially impurities. Thus, as an insulation film 6 can be formed at a high temperature, it is possible to form an insulation thin film of a uniform film thickness which does not depend upon semiconductor surface impurity concentration and to simultaneously and entirely realize thin junction and high efficient activation of the source and drain.

12. 发明专利

JPH03266465A SOLID-STATE IMAGE SENSING DEVICE 失效
公开(公告)号：JPH03266465A
公开(公告)日：1991-11-27
申请号：JP6417090
申请日：1990-03-16
申请人： HITACHI LTD
发明人： NAKAI MASAAKI , SATO AKIRA , AOKI SHIGERU , KONAME KANJI , OYU SHIZUNORI , HIRAIWA ATSUSHI
IPC分类号： H01L27/148 , H04N5/335 , H04N5/359 , H04N5/365 , H04N5/367 , H04N5/369 , H04N5/372 , H04N5/374
摘要： PURPOSE:To suppress crystal defects caused by contaminants by a method wherein a crystal defect layer of high density is positively formed inside an overflow drain. CONSTITUTION:A P-type well layer 22 is formed on an N-type Si substrate 21, a P -type double well and an N-type diffusion layer are selectively formed on a vertical CCD channel section, a first gate oxide film 31 is deposited on the surface, a photoresist 33 is formed on a region other than an overflow drain region 32, As or F ions are implanted into the region 32 using the photoresist 33 as a mask to form an impurity layer 34. In succession, the gate oxide film 31 in the region 32 is removed, the photoresist 33 is removed, polycrystalline poly-Si 2 and 27 serving as a first gate electrode are selectively built, a second gate 28 and a third gate 29 are formed to finish the formation of an element, and an overflow drain 26 is formed through diffusion of impurities from the first poly-Si. A crystal defect layer 30 of high density grown from the damaged layer 34 in an oxidation process is formed inside the overflow drain region. By this setup, crystal defects can be prevented.

13. 发明专利

JPH02119173A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02119173A
公开(公告)日：1990-05-07
申请号：JP27065288
申请日：1988-10-28
申请人： HITACHI LTD
发明人： GOSHIMA HIDEKAZU , KASHU NOBUYOSHI , OYU SHIZUNORI , SUZUKI TADASHI
IPC分类号： H01L21/761 , H01L21/74 , H01L21/76 , H01L21/8242 , H01L27/08 , H01L27/10 , H01L27/108 , H01L29/47 , H01L29/78 , H01L29/861 , H01L29/872
摘要： PURPOSE:To suppress the leakage current of a p-n junction and save the power consumption and realize high speed operation by a method wherein a first buried impurity layer of p-type which is the conductivity type of a substrate and an n-type second buried impurity layer are formed and the higher maximum impurity concentration is given to the second impurity layer. CONSTITUTION:After an element isolation oxide film 5 is formed on a substrate 4, boron B ions are implanted to form a B-implanted layer 6. Then a first buried impurity layer 7 of p-type which is the conductivity type of the substrate 4 is formed and, in a region deeper than the layer 7, a second buried layer 8 having the higher maximum impurity concentration is formed. If the impurity is activated by annealing in a nitrogen atmosphere, the layer 6, layer 7 and layer 8 are turned into a p-type layer, a p-type buried layer and an n-type buried layer respectively. Then As ions are implanted and a high impurity concentration n-type region 9 is formed in the surface of the substrate 4 by annealing to form a p-n junction. With this constitution, the surface integral of the leakage current of the p-n junction can be suppressed and the power consumption of an LSI can be saved and the high speed operation of the LSI can be realized.

14. 发明专利

JPS6444078A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6444078A
公开(公告)日：1989-02-16
申请号：JP19969787
申请日：1987-08-12
申请人： HITACHI LTD
发明人： SUZUKI TADASHI , KASHU NOBUYOSHI , OYU SHIZUNORI , GOSHIMA HIDEKAZU
IPC分类号： H01L39/22 , H01L21/3205 , H01L23/52
摘要： PURPOSE:To eliminate a stress at least to a semiconductor substrate even if a composite structure of a superconductor and a semiconductor is cooled to a super-low temperature by providing a stress buffer layer between a superconducting material section and a semiconductor section. CONSTITUTION:A layer 2 for buffering a distortion or a stress is provided between a superconductor 3 and a semiconductor 1. That is, the stress due to the difference of the thermal expansion coefficients of both the materials is absorbed by the buffer layer provided between both the materials to eliminate the distortion, stress in both the materials. Thus, even if a composite structure of the superconductor and the semiconductor is cooled to a super-low temperature, no stress is applied to the superconductor and the semiconductor. Accordingly, a high speed semiconductor device having high reliability can be performed.

15. 发明专利

JPS6365630A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6365630A
公开(公告)日：1988-03-24
申请号：JP20794286
申请日：1986-09-05
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： WADA YASUO , OGA KAZUHIRO , ISHIKAWA AKIRA , OYU SHIZUNORI , KASHU NOBUYOSHI
IPC分类号： H01L21/316 , H01L21/768
摘要： PURPOSE:To improve the ion stopping power while preventing the film stress from occurring by a method wherein a coated film is filled with the most com pact fine particles. CONSTITUTION:A silicon substrate 1 is spin-coated with ethanol solution of 5 % silanol (Si(ON4)) containing 3 weight % of SiO2 fine particles in diameter of 0.1 mum at 3000 rpm to form a coated glass layer 3 containing fine particles in grooves and then the substrate 1 is annealed in a baking furnace kept at 200 deg.C for 20 minutes. At this time, inside of grooves is thickly coated with the solution in around 0.4mum while projections are thinly coated with the solution in around 0.05 mum. The film thickness ratio between upper and lower step difference depending on the depth and width etc., can be specified as around 1:10. The total film thickness of around 2 mum can be attained by coating glass film containing fine particles three times. At this time, glass films 4-6 spin- coated on the silicon substrate 1 respectively at 2000 rpm are baked at around 200 deg.C for 30 minutes to be dehydrated for condensation. Through these procedures, the gas releasing amount can be minimized even if the substrate 1 is annealed at 900 deg.C for around 20 minutes after coating process.

16. 发明专利

JPS62239576A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62239576A
公开(公告)日：1987-10-20
申请号：JP8203086
申请日：1986-04-11
申请人： HITACHI LTD
发明人： SUZUKI TADASHI , KASHU NOBUYOSHI , OYU SHIZUNORI
IPC分类号： H01L29/43 , H01L21/28 , H01L29/78
摘要： PURPOSE:To provide a chemical resistance for a metallic silicide of low chemical resistance by forming a carbonized metal film above a silicide film in a semiconductor device using a metallic silicide. CONSTITUTION:A carbonized metal film 3 and a metallic silicide film 2 are formed on a semiconductor substrate 1 in order from the surface. As the carbonized metal film, titanium carbide which has a low specific resistance and a high resistance to hydrofluoric acid is used. Thus, the metallic silicide film 2 can be provided with a resistance to hydrofluoric acid without causing an increase in resistance.

17. 发明专利

JPS6262555A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6262555A
公开(公告)日：1987-03-19
申请号：JP20152685
申请日：1985-09-13
申请人： HITACHI LTD
发明人： OYU SHIZUNORI , KOBAYASHI NOBUYOSHI , HASHIMOTO NAOTAKA , KASHU NOBUYOSHI , WADA YASUO
IPC分类号： H01L29/43 , H01L21/28
摘要： PURPOSE:To obtain a semiconductor device which has less irregular electric characteristics by selecting a metal silicide having less layer resistance variation for an impurity for forming a diffused layer, and forming a plurality of silicide layers of different materials on a different conductive type diffused layer. CONSTITUTION:A tungsten silicide film 3 is formed on an N-type diffused layer 2 on the surface of a silicon substrate 1 formed by implanting arsenic and phosphorus, and a titanium silicide film 5 is formed on a P-type diffused layer 4 formed by implanting boron. The layer resistance variations of the both silicide films on the diffused layers can be suppressed to 10% or less in the film 3 on the layer 2, and can be almost eliminated in the film 5 on the layer 4. In other words, the layer resistance of the silicide films can be maintained almost constant irrespective of a method of forming the diffused layer and the silicide film and following heat treatment.

18. 发明专利

JPS6261346A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6261346A
公开(公告)日：1987-03-18
申请号：JP19941085
申请日：1985-09-11
申请人： HITACHI LTD
发明人： OYU SHIZUNORI , KASHU NOBUYOSHI , SUZUKI TADASHI , WADA YASUO
IPC分类号： H01L21/768 , H01L21/28 , H01L21/3205 , H01L21/336 , H01L29/78
摘要： PURPOSE:To form a junction after the opening of a contact hole to be thin and of low resistance, by forming a titanium nitride film and a titanium silicide film in a self-matching manner after the contact hole is opened. CONSTITUTION:After a contact hole is opened, a titanium metal film 10 is deposited, and then a titanium silicide film 8 is formed by heat treatment on the surfaces of a substrate 1 and a diffused layer 3 in a portion wherein the contact hole is opened. At this time, the titanium metal 10 deposited on a passivation film 4 and a field oxide film 2 is left in an unreacted state. Next, the unreacted titanium metal film 10 is removed selectively, and impurity ions 11 of the same conductivity type as the diffused layer 3 are implanted. Thereafter, heat treatment is applied in the atmosphere of nitrogen (or in the atmosphere of gas containing nitrogen atoms) to activate a titanium nitride film 7 and impurities on the surface of the titanium silicide film 8, so as to form an impurity-doped layer 9.

19. 发明专利

JPS61284919A METHOD FOR ION IMPLANTATION 失效
公开(公告)号：JPS61284919A
公开(公告)日：1986-12-15
申请号：JP12601385
申请日：1985-06-12
申请人： HITACHI LTD
发明人： OYU SHIZUNORI , KASHU NOBUYOSHI , WADA YASUO , TAMURA MASAO , SUZUKI TADASHI , SHINTANI AKIRA , OKUDAIRA HIDEKAZU , YADORI SHOJI
IPC分类号： H01L21/266 , H01L21/265
摘要： PURPOSE:To obtain a mask structure which is used for high-energy ion implantation at over several 100KeV, by regulating the mask construction and the total mask thickness, thereby enabling the control of the distribution of the ion species to be implanted into the substrate underneath the mask. CONSTITUTION:A first amorphous film 2 is formed on the surface of a substrate 1 to be subjected to implantation (a). Then, a metal film 3 of a large mass number is formed (b), and a second amorphous film 4 is formed (c). Thereafter, by the conventional photoetching process, said second amorphous film 4 and said metal film 3 on the implantation region 5 are removed (d). High-energy ions 6a are implanted to this sample, forming an implantation layer 7 (e). At this time, by changing the distances between the substrate 1 surface and the metal films 3a and 3b, the implantation layer 7 having different concentrations and depths of implanted ion species can be formed in the substrate 1 by one ion implantation.

20. 发明专利

JPS61248476A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61248476A
公开(公告)日：1986-11-05
申请号：JP8853285
申请日：1985-04-26
申请人： HITACHI LTD
发明人： OYU SHIZUNORI , SUGASHIRO SHIYOUJIROU , HASHIMOTO NAOTAKA , KASHU NOBUYOSHI , SUZUKI TADASHI , WADA YASUO
IPC分类号： H01L29/78 , H01L21/225 , H01L21/324
摘要： PURPOSE:To form an N-type diffused layer with a double-layer composition which has a high concentration is a shallow region and has a low concentration in a deep region in a silicon substrate effectively by a method wherein phosphorus ions are implanted into a silicide film only and, after a silicon oxide film is formed, annealing is applied. CONSTITUTION:After a metal film is formed on a P-type silicon substrate 1, a silicide film 2 is formed by annealing. Then phosphorus ions are implanted into the silicide film 2 only with a high concentration and a silicon oxide film 4 is formed on the silicide film 2. Finally, annealing is carried out to diffuse the phosphorus implanted in the silicide film 2 into the silicon substrate 1 and a phosphorus diffused layer 5 is formed. The N-type carrier concentration distribution 6 of the phosphorus diffused layer 5 in the silicon substrate 1 is obtained as a two-step distribution consisting of a high concentration part 7 in a shallow region and a low concentration part 8 in a deep region. The junction depth of this double-layer N-type diffused layer is mainly determined by the relatively deep low concentration diffused layer and a required depth can be obtained by optionally selecting the temperature and period of the annealing.

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