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1. 发明专利

JPH07161988A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH07161988A
公开(公告)日：1995-06-23
申请号：JP30772993
申请日：1993-12-08
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SHIMIZU AKIHIRO , OYU SHIZUNORI , OOKI NAGATOSHI , ISHIDA HIROSHI , YAMANAKA TOSHIAKI , HASHIMOTO KOJI
IPC分类号： H01L29/43 , H01L21/265 , H01L21/336 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/786
摘要： PURPOSE:To provide a manufacturing method by which thin junction source and drain of a MIS type field-effect transistor are effectively formed and gate insulation breakdown strength is not deteriorated. CONSTITUTION:A manufacturing method includes a step of introducing impurities for forming source and drain regions 5 after a gate electrode 3 is patterned; and a step of forming a thin film insulation film at a high temperature for a short time by a rapid heating and cooling method and simultaneously activating initially impurities. Thus, as an insulation film 6 can be formed at a high temperature, it is possible to form an insulation thin film of a uniform film thickness which does not depend upon semiconductor surface impurity concentration and to simultaneously and entirely realize thin junction and high efficient activation of the source and drain.

2. 发明专利

JPS6365630A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6365630A
公开(公告)日：1988-03-24
申请号：JP20794286
申请日：1986-09-05
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： WADA YASUO , OGA KAZUHIRO , ISHIKAWA AKIRA , OYU SHIZUNORI , KASHU NOBUYOSHI
IPC分类号： H01L21/316 , H01L21/768
摘要： PURPOSE:To improve the ion stopping power while preventing the film stress from occurring by a method wherein a coated film is filled with the most com pact fine particles. CONSTITUTION:A silicon substrate 1 is spin-coated with ethanol solution of 5 % silanol (Si(ON4)) containing 3 weight % of SiO2 fine particles in diameter of 0.1 mum at 3000 rpm to form a coated glass layer 3 containing fine particles in grooves and then the substrate 1 is annealed in a baking furnace kept at 200 deg.C for 20 minutes. At this time, inside of grooves is thickly coated with the solution in around 0.4mum while projections are thinly coated with the solution in around 0.05 mum. The film thickness ratio between upper and lower step difference depending on the depth and width etc., can be specified as around 1:10. The total film thickness of around 2 mum can be attained by coating glass film containing fine particles three times. At this time, glass films 4-6 spin- coated on the silicon substrate 1 respectively at 2000 rpm are baked at around 200 deg.C for 30 minutes to be dehydrated for condensation. Through these procedures, the gas releasing amount can be minimized even if the substrate 1 is annealed at 900 deg.C for around 20 minutes after coating process.

3. 发明专利

JPH07283324A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH07283324A
公开(公告)日：1995-10-27
申请号：JP6831794
申请日：1994-04-06
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： YAMASHITA HISAOMI , KISU TERUAKI , OYU SHIZUNORI , YADORI SHOJI , YOSHIGAMI JIRO , KURE TOKUO
IPC分类号： H01L21/76 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To form a high-quality memory which is suitable for such characteristics as the leakage current of an element, dielectric strength of a gate, etc., and can be suitably formed by depressing the surface of a semiconductor in a memory forming area by selective oxidation. CONSTITUTION:A silicon oxide film 2 and silicon nitride film 3 are continuously deposited on the surface of a silicon substrate 1. Then a resist material is left on the surface of the film 3 except a memory array forming part by photolithography and the film 3 is removed from the memory array forming part by dry etching. After removing the film 3, the resist material used for the dry etching as a mask is removed. When the substrate 1 is oxidized thereafter, an oxide film 4 is selectively fornted in the memory array forming part, because the other part of the substrate 1 than the memory array forming part is not oxidized due to the silicon nitride film 3 covering the substrate 1. After forming the oxide film 4, the silicon nitride film 3 and silicon oxide films 2 and 4 are removed by wet etching. Consequently, only the memory array forming part is depressed from the other part. Therefore, a high-quality memory can be formed by using the depressed part.

4. 发明专利

JPH07142599A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH07142599A
公开(公告)日：1995-06-02
申请号：JP28305193
申请日：1993-11-12
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： YAMASHITA HISAOMI , KISU TERUAKI , OYU SHIZUNORI , YADORI SHOJI , YOSHIGAMI JIRO , KURE TOKUO
IPC分类号： H01L27/10 , H01L21/324 , H01L21/8242 , H01L27/108
摘要： PURPOSE:To prevent OSF and to prevent the deterioration of refresh characteristics by diffusing oxygen in an Si substrate outward beforehand so as to prevent the deposition of the oxygen before annealing for well formation. CONSTITUTION:At first, high-temperature annealing is performed in an N2 atmosphere, and oxygen in an Si substrate 1 is diffused outward. SiO2 2 and Si3N4 3 are continuously deposited, a resist material is made to remain at a part other than a memory-array forming part by a photolithography step, the Si3N4 is machined, the resist is removed and only a memory step part is located at the lower position. When the Si substrate 1 is oxidized by a high-voltage oxidizing method, a part other than the methory array part is not oxidized because the part is covered with the Si3N4 3. An oxide film 4 is formed selectively only at the memory-array forming part. When the Si3N4 3 and the SiO2 2 are removed, only the memory array part is brought to the lower position in comparison with the other region. Thus, OSF generated in association with a step for selectively oxidizing the surface of a semiconductor in the memory forming region can be prevented.

5. 发明专利

JPH11204783A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREFOR 失效
公开(公告)号：JPH11204783A
公开(公告)日：1999-07-30
申请号：JP276098
申请日：1998-01-09
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ISHIDA HIROSHI , OYU SHIZUNORI , OOKI NAGATOSHI , SHIMIZU AKIHIRO , SHIBA TAKEO
IPC分类号： H01L29/78 , H01L21/265 , H01L21/322
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method in which increased speed diffusion or re-distribution of a punch through stopper layer formed for suppression of a short channel effect is reduced, and an inverted short channel effect is suppressed. SOLUTION: A region 17 where fluorine exists is provided at a region of a p-type conductive punch through stopper layer 16 formed in a p-type conductive silicone substrate 11. As fluorine is captured by excessive failure which is introduced in the silicone substrate when a high density source and a drain diffusion layer are formed, increased speed diffusion or re-distribution of a punch through stopper layer can be reduced, an inverted short channel effect is suppressed and a short channel effect is improved. Additionally a long term reliability represented by a hot carrier effect can be improved.

6. 发明专利

JPH06112157A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREFOR 失效
公开(公告)号：JPH06112157A
公开(公告)日：1994-04-22
申请号：JP25614492
申请日：1992-09-25
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SATO AKIRA , KAWAMOTO YOSHIFUMI , OYU SHIZUNORI , YOKOYAMA NATSUKI , KONO MASAKAZU
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L21/90
摘要： PURPOSE:To form a metal silicide film not depending on a size of a contact hole by forming a thin metal film after the contact hole is opened on an insulation film, having it subjected to thermal treatment in a gas atmosphere containing nitrogen while forming a metal silicide film mainly containing the thin metal film at the bottom of the contact hole. CONSTITUTION:Photo resist is removed and a thin metal film 30 is formed by means of sputtering. In forming the thin metal film 30 by sputtering, thickness at the bottom of a contact hole 28 having a smaller aspect ratio due to a shadowing effect is smaller than that at the bottom of a contact hole 29. Thermal treatment at 800 deg.C is performed in a N2 atmosphere to form the thin metal film 3 into metal silicide film 31, 32. Thus thickness of metal silicide films 25, 31 at the bottom of the contact hole 28 and thickness of metal silicide films 25, 32 at the bottom of the contact hole 29 are almost constant.

7. 发明专利

JPH06349918A METHOD OF EVALUATING SEMICONDUCTOR 失效
公开(公告)号：JPH06349918A
公开(公告)日：1994-12-22
申请号：JP14032893
申请日：1993-06-11
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TAKAHAMA TAKASHI , OYU SHIZUNORI , USUI HIROO , YOSHIGAMI JIRO
IPC分类号： H01L21/66
摘要： PURPOSE:To enable the resistance of an impurity introduced layer to be measured even if a punch-through phenomenon is generated by a probe in the impurity introduced layer by a method wherein a specimen whose carrier density is 1/10 as low as or less than the maximum carrier density of the impurity introduced layer and which is deeper than the impurity introduced layer is used. CONSTITUTION:The resistance of a veery shallow impurity introduced layer 1 formed on the surface region of a semiconductor substrate is measured through a two-probe method or a four-probe method 6. That is, a region 2 has a carrier density 1/10 as low as or less than the maximum carrier density of the impurity introduced layer 1, is of the same conductivity type as the impurity introduced layer 1, and deeper than the impurity introduced layer 1, and a specimen which is possessed of the region 2 concerned in a semiconductor substrate of conductivity type different from that of the impurity introduced layer 1 is used to make a measurement. By this setup, when measurement is conducted through a four- probe method or a two-probe method, the resistance of the impurity-introduce layer 1 can be measured even if a punch-through phenomenon is generated by a probe in the impurity-introduced layer 1.

8. 发明专利

JPH05206048A LAMP ANNEAL DEVICE 失效
公开(公告)号：JPH05206048A
公开(公告)日：1993-08-13
申请号：JP1475892
申请日：1992-01-30
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KATO HIDEAKI , OYU SHIZUNORI , KOGANO MASAYOSHI
IPC分类号： H01L21/26 , H01L21/324
摘要： PURPOSE:To enable the heating of a board to be processed to be performed equally so as to reduce the occurrence of defects by arranging the constitution such that cold atmospheric gas does not contact directly with the board to be processed inside the atmosphere wherein it is installed. CONSTITUTION:This is a lamp annealing device of such constitution that a board 1 to be processed is installed in a heat treatment vessel 2, and that a lamp 6 is arranged in the position opposite to this board, heating chambers 8a and 8b are coupled with the heat treatment vessel 2, and the atmosphere to be introduced into the atmosphere wherein the board 1 to be heat-treated is installed is preheated in the heating chambers 8a and 8b, and the preheated atmospheric gas is introduced into the heat-treatment vessel 2. Moreover, the atmospheric gas not preheated at cooling is introduced from the heating chambers 8a and 8b.

9. 发明专利

JP2006252648A Dynamic random access memory device and test method therefor 有权
标题翻译：动态随机存取存储器及其测试方法
公开(公告)号：JP2006252648A
公开(公告)日：2006-09-21
申请号：JP2005066657
申请日：2005-03-10
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： MORI TOMONORI , YAMADA RENICHI , TSUKADA SHUICHI , OYU SHIZUNORI
IPC分类号： G11C29/56 , G01R31/28 , G01R31/30 , G11C11/401 , G11C29/44
CPC分类号： G11C29/50 , G11C11/401 , G11C29/50016
摘要： PROBLEM TO BE SOLVED: To screen a so-called variable retention time (VRT) defect caused by the fact that a data retention time varies like random telegraph noise in DRAM. SOLUTION: A bit which may cause a retention defect of a data retention capability resulting from random changes with time is screened by repeating a pause refresh test for checking a data retention function in the whole chip surface and the whole bits by an optimized frequency. COPYRIGHT: (C)2006,JPO&NCIPI

10. 发明专利

JP2006040991A Method of evaluating semiconductor device and manufacturing method thereof 审中-公开
标题翻译：评估半导体器件的方法及其制造方法
公开(公告)号：JP2006040991A
公开(公告)日：2006-02-09
申请号：JP2004215183
申请日：2004-07-23
申请人： Elpida Memory Inc , Hitachi Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所
发明人： TAKATO ATSUKO , NOZOE MARI , OYU SHIZUNORI
IPC分类号： H01L21/66 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/108
CPC分类号： H01L22/14 , G01R31/2653 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a technology which makes it possible to evaluate the leak characteristics distribution in a pn junction in the middle of manufacturing process of a semiconductor device having the pn junction, and to rapidly feed back the evaluation results to decision making of manufacturing process conditions. SOLUTION: For a wafer in the middle of manufacturing process, an electron beam is irradiated several times on the surface of the wafer whereon a plug is exposed at prescribed intervals under such a condition that the pn junction may be reverse-biased. Monitoring the charged potential of the surface of the plug, the electron beam irradiation conditions are changed to such ones that the charged potential may come within a desired range. Under such irradiation conditions, a secondary electron signal of a circuit pattern is obtained and the leak characteristics are evaluated. Since the charged potential in the pn junction is relaxed according to the size of the leakage current within intermittent time, the leak characteristics are evaluated from the brightness signal of a potential contrast image. Thus, by measuring the charged potential and making it within a desired range, the evaluation results reflect a state in actual operation and thereby the accuracy improves. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够在具有pn结的半导体器件的制造过程中评估pn结中的泄漏特性分布的技术，并且将评估结果快速反馈到制造工艺条件的决策。解决方案：对于在制造过程中间的晶片，在pn结可以被反向偏置的条件下，以规定的间隔将电子束照射在晶片的表面上，在该表面上暴露一个电极。监测插头表面的带电电位，将电子束照射条件改变为充电电位可能在期望范围内的条件。在这种照射条件下，获得电路图案的二次电子信号，并评价泄漏特性。由于根据间歇时间内的漏电流的大小使pn结中的充电电位松弛，所以根据潜在对比度图像的亮度信号来评价泄漏特性。因此，通过测量充电电位并使其在期望的范围内，评价结果反映实际操作中的状态，从而提高精度。版权所有（C）2006，JPO＆NCIPI

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