专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明专利

JPS618448B2 JPS618448B2 - 失效
公开(公告)号：JPS618448B2
公开(公告)日：1986-03-14
申请号：JP2748180
申请日：1980-03-04
申请人： Fujitsu Ltd
发明人： AOKI TAKASHI
IPC分类号： G06F7/508 , G06F7/52 , G06F7/535
CPC分类号： G06F7/535

12. 发明专利

JPS6049946B2 失效
公开(公告)号：JPS6049946B2
公开(公告)日：1985-11-06
申请号：JP8918681
申请日：1981-06-10
申请人： FUJITSU LTD
发明人： AOKI TAKASHI , MYAJIMA SHIGERU , NODA KATSUNOBU , YAMAMURO YOSHIO
IPC分类号： G06F13/38 , G06F5/06 , G06F12/08 , G06F13/16

13. 发明专利

JPS6032223B2 失效
公开(公告)号：JPS6032223B2
公开(公告)日：1985-07-26
申请号：JP9763479
申请日：1979-07-31
申请人： FUJITSU LTD
发明人： IWATO MASATAKE , AOKI TAKASHI
IPC分类号： G06F12/16 , G11C29/00

14. 发明专利

JPS6043771A BUFFER MEMORY CONTROL SYSTEM 失效
公开(公告)号：JPS6043771A
公开(公告)日：1985-03-08
申请号：JP15177383
申请日：1983-08-20
申请人： FUJITSU LTD
发明人： AOKI TAKASHI
IPC分类号： G06F15/16 , G06F15/177
摘要： PURPOSE:To prevent an overflow of an invalidating stack register of each buffer memory device by inhibiting transmission of the invalidating signal of a data block for each store when an access is given to a large amount of data all at once. CONSTITUTION:In case the store accessess are given continuously to a main memory (not shown in the figure) from a processor #0, both head and end addresses of a store access area are set to a head address register SSA201 and an end register SEA202 provided within a buffer memory device #0 of a processor #0 and then sent to the memory device #1 in order to invalidate the corresponding block within a buffer memory device #1 of a processor #1 for example. The memory device #1 sets each address information to head and end address registers 211 and 212 respectively and sends an invalidating address MBIA to a multiplexer 6.

15. 发明专利

JPS59123949A Processing system in error occurrence 失效
标题翻译：处理系统在错误发生
公开(公告)号：JPS59123949A
公开(公告)日：1984-07-17
申请号：JP23278482
申请日：1982-12-29
申请人： Fujitsu Ltd
发明人： KUBOU KATSUMI , AOKI TAKASHI
IPC分类号： G06F11/32 , G06F11/00 , G06F11/07
CPC分类号： G06F11/0703
摘要： PURPOSE:To match continuously an FF for error control and an FF for error display with each other by supplying the output of a checking circuit to the FF for error control and also supplying it directly to the FF for error display. CONSTITUTION:The FF3 for error display and the FF4 for error control are both reset. The checking circuit 2 outputs an error signal with logic 1 when detecting error occurrence. When a signal CLOFF has logic 0, a clock signal CLKA is generated. This signal sets the error signal with a logic 1 to the FF3 for error display and also sets the error control FF4 at the same time. When the FF4 is set, a signal ERR1 has logic 1 and the signal CLKA is ceased, so that the contents of a register 1 shows the error occurrence continuously.
摘要翻译：目的：通过向FF提供检查电路的输出进行错误控制，并将其直接提供给FF进行错误显示，连续匹配用于错误控制的FF和用于错误显示的FF。构成：用于错误显示的FF3和错误控制的FF4都被复位。当检测到错误发生时，检查电路2输出具有逻辑1的错误信号。当信号CLOFF为逻辑0时，产生时钟信号CLKA。该信号将错误信号以逻辑1设置为FF3进行错误显示，并同时设置错误控制FF4。当FF4被置位时，信号ERR1具有逻辑1并且信号CLKA被停止，使得寄存器1的内容连续显示错误。

16. 发明专利

JPS5952351A Instruction retrial system 失效
标题翻译：指导性返回系统
公开(公告)号：JPS5952351A
公开(公告)日：1984-03-26
申请号：JP16339982
申请日：1982-09-20
申请人： Fujitsu Ltd
发明人： MARUO AKIHIRO , AOKI TAKASHI
IPC分类号： G06F11/14
CPC分类号： G06F11/14
摘要： PURPOSE:To perform a check to avoid use of the undesired information for an instruction retrial which is carried out when an error is detected during the information processing, by comparing a read address given from an arithmetic result storing register with a write address to be applied to an external storage device. CONSTITUTION:A comparator CMP compares a read address of an arithmetic result storing register ARR with an address of an external storage device MM to check the coincidence in the form of an input. The output of the CMP is defined as ''absence'' since the CMP usually obtains the coincidence: while the output is defiend as ''presence'' when no coincidence is obtained. Therefore a flag register FLG can be turned on when the discordance of address is detected by inverting the output of the CMP through a polarity inverter INV. A central processor CPU always monitors the register FLG when an instruction retrial is carried out for detection of errors. Then the retrial is discontinued when the FLG is turned on since it is possible enought that the using information is transformed. Furthermore the previous information is found out by another means.
摘要翻译：目的：为了执行检查，以避免在信息处理期间检测到错误时执行的指令重试中使用不需要的信息，通过将从算术结果存储寄存器给出的读取地址与要应用的写入地址进行比较到外部存储设备。构成：比较器CMP将算术结果存储寄存器ARR的读取地址与外部存储器件MM的地址进行比较，以检查输入形式的一致性。 CMP的输出被定义为“不存在”，因为CMP通常获得重合：当没有获得符合时，输出被定义为“存在”。因此，当通过极性反相器INV反相CMP的输出来检测到地址不一致时，可以打开标志寄存器FLG。当执行指令重试以检测错误时，中央处理器CPU总是监视寄存器FLG。然后，当FLG打开时，重试被停止，因为可能足以使用信息被转换。此外，以前的信息是通过另一种手段发现的。

17. 发明专利

JPS5848940B2 JPS5848940B2 - 失效
标题翻译：空值
公开(公告)号：JPS5848940B2
公开(公告)日：1983-11-01
申请号：JP7960578
申请日：1978-06-30
申请人： Fujitsu Ltd
发明人： SAGARA HISAJIRO , AOKI TAKASHI
IPC分类号： G06F11/14 , G06F11/00 , G06F11/34

18. 发明专利

JPS5847785B2 JPS5847785B2 - 失效
公开(公告)号：JPS5847785B2
公开(公告)日：1983-10-25
申请号：JP8001179
申请日：1979-06-25
申请人： Fujitsu Ltd
发明人： AOKI TAKASHI
IPC分类号： G06F12/08 , G06F12/10 , G06F13/00

19. 发明专利

JPS5856037A CENTRAL PROCESSING UNIT FOR MICROPROGRAM CONTROL 失效
公开(公告)号：JPS5856037A
公开(公告)日：1983-04-02
申请号：JP15414081
申请日：1981-09-29
申请人： FUJITSU LTD
发明人： TAKADA HIROSHI , AOKI TAKASHI
IPC分类号： F02B75/02 , G06F9/22 , G06F12/04
摘要： PURPOSE:To access a microprogram memory smoothly by performing two-cycle operation successively through hardware without generating a deliberate microprogram. CONSTITUTION:Registers RG-A and RG-B are connected to an arithmetic logical circuit and also connected to a main storage MS. Further, a memory address register MSAD, a register LG stored with the length of an operand, and a register ACD for indicating a direction of access are connected to the access control circuit MAC of the main storage. Then, the registers MSAD, LG, and ACD are set by a micro-instruction, so it is evident that the main storage MS crosses a boundary BD. Consequently, a CPU is controlled by signals EX1T and EX2T, obtained by a decoder DEC, through the circuit MAC, so even if a microprogram attains access crossing the boundary, a programmer writes the program smoothly without being aware of that.

20. 发明专利

JPS57205882A BUFFER MEMORY CONTROLLING SYSTEM 失效
公开(公告)号：JPS57205882A
公开(公告)日：1982-12-17
申请号：JP8918681
申请日：1981-06-10
申请人： FUJITSU LTD
发明人： AOKI TAKASHI , MIYAJIMA SHIGERU , NODA KATSUNOBU , YAMAMURO YOSHIO
IPC分类号： G06F13/38 , G06F5/06 , G06F12/08 , G06F13/16
摘要： PURPOSE:To reduce the time required for fetching commands and to prevent occurrences of overrun when fetching is operated from a channel, by permitting writing in a buffer memory from the main memory only under apecified conditions. CONSTITUTION:A signal CPUMOD which indicates that accessing is performed from a CPU and another signal FETCH which indicates that fetching is performed from the CPU are inputted into an AND circuit. A signal IOMOD which indicates that accessing is performed from a channel and another signal CMDFETCH which indicates that an fetching operation is performed from the channel are inputted into another AND circuit 2. The output of these AND circuits is inputted into an OR circuit 4 and the output of the OR circuit 4 is inputted into a flip-flop 5 which controes which data supplied from a main memory is to be written in a buffer memory or not. The output of the flip-flop 5 is inputted into an AND circuit 3 and becomes a writing timing signal WBS to the buffer memory.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式