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    • 6. 发明专利
    • Logging information guarantee system
    • 登录信息保障系统
    • JPS61133448A
    • 1986-06-20
    • JP25612784
    • 1984-12-04
    • Fujitsu LtdNippon Telegr & Teleph Corp
    • YAMAZAKI HIROMOCHIWATARAI HIROSHI
    • G06F11/34G06F11/07
    • G06F11/073G06F11/0703
    • PURPOSE:To prevent processing contradiction from being caused at malfunction and edition when a real medium is read and processed by clarifying the relation before and after logging information blocks written on the real medium. CONSTITUTION:When it is supposed that a system-down takes place and write of the logging information from a memory buffer MB is restarted from a block 15, the content of blocks 13, 14 is lost without being written on the real medium and after system relieve leading (RIPL) takes place, new logging information is written on the real medium from the memory buffer MB as the block 15. In reading the magnetic tape MT for processing by a logging magnetic tape reference program, since '0' is set to an identification section 15b of the own block 15 regardless of '1' representing overflow display to the block 12, the possibility of mis-recognition that the overflow information is recorded from the block just before is precluded.
    • 目的:通过澄清在实际介质上记录信息块之前和之后的关系来读取和处理真实介质时,防止处理在故障和编辑过程中产生的冲突。 构成:当假设发生系统关闭并且从块15重新开始从存储器缓冲器MB写入记录信息时,块13,14的内容在没有被写入真实介质上且在系统之后被丢失 缓冲引线(RIPL)发生时,将新的记录信息作为块15从存储缓冲器MB写入实际介质上。在读取磁带MT以进行记录磁带参考程序处理时,由于将“0”设置为 自身块15的识别部分15b,不管表示对块12的溢出显示的“1”,排除了刚刚从块中记录溢出信息的可能性。
    • 7. 发明专利
    • Error report processing system
    • 错误报告处理系统
    • JPS61125651A
    • 1986-06-13
    • JP24684584
    • 1984-11-21
    • Fujitsu Ltd
    • SEKI KAZUHISA
    • G06F11/07G06F11/10G06F12/16
    • G06F11/073G06F11/0703G06F11/10
    • PURPOSE:To reduce the possibility of developing to an error of plural bits by preparing a status where the report about the error is submitted positively in case of a fault related to a hard error, i.e., a fixed fault of an element among the faults of a memory. CONSTITUTION:A transfer circuit 1 receives a report on the generation of a 1-bit error when the transfer is over with the final data. Thus an MPU7 sets the contents of a register 5 to an address register in the circuit 1. The value of the register 5 is equal to the address where the 1-bit error is produced and therefore the MPU7 uses said address to read a memory 3. Then the MPU7 writes the read data (normal data containing no error) to the same address, then reads it again in the same address. When an error occurs at this time, it is decided as a hard error. When the contents of the register 5 are not included in a register file 6, the MPU7 decides said error as the first one and sets a fault end status to the circuit 1 to indicate the end of the data transfer.
    • 目的:通过准备在出现与硬错误有关的故障的情况下正确提交关于错误的报告的状态,即在故障中的元件的固定故障之间,减少发展为多位错误的可能性 一个记忆 构成:转移电路1接收关于当最终数据传送结束时产生1位错误的报告。 因此,MPU7将寄存器5的内容设置到电路1中的地址寄存器。寄存器5的值等于产生1位错误的地址,因此MPU7使用所述地址读取存储器3 然后,MPU7将读取的数据(不含错误的正常数据)写入相同的地址,然后再次读取相同的地址。 当此时发生错误时,会将其确定为硬错误。 当寄存器5的内容不包括在寄存器文件6中时,MPU7将所述错误判定为第一个,并且将电路1的故障结束状态设置为指示数据传送的结束。
    • 8. 发明专利
    • Fault information collecting system
    • 故障信息收集系统
    • JPS61122760A
    • 1986-06-10
    • JP24336984
    • 1984-11-20
    • Nec Corp
    • AKICHI YASUHIDE
    • G06F11/34G06F11/07
    • G06F11/0703
    • PURPOSE:To read out information from a logical device automatically by reading out the state of the logical device by an information collector when the status of the logical device coincides with a previously set stopping condition and the logical device stops. CONSTITUTION:A condition for a maintenance man to stop the logical device 1 at a proper point of time for fault information collection at the intermittent generation of faults or the generation of an unaccoutable fault is inputted from an input part 20. In the logical device 1, the contents of a state displaying circuit 10 displaying the state of the logical device 1 are compared with that of a storage circuit 11 storing the previously set stopping condition by a comparator 12, and both the contents coincide with each other, the operation of the logical device is stopped.
    • 目的:当逻辑设备的状态与先前设置的停止条件一致并且逻辑设备停止时,通过从信息收集器读出逻辑设备的状态,自动从逻辑设备中读出信息。 规定:从输入部20输入维护人员在适当的时间点停止逻辑设备1的故障信息收集状态,或者产生不可复原故障的状况。逻辑设备1 将显示逻辑设备1的状态的状态显示电路10的内容与比较器12存储先前设置的停止条件的存储电路11的内容进行比较,并且两个内容彼此一致, 逻辑设备停止。
    • 9. 发明专利
    • Circuit for detecting computer runaway
    • 检测计算机RUNAWAY的电路
    • JPS61109151A
    • 1986-05-27
    • JP22964784
    • 1984-10-31
    • Shinko Electric Co Ltd
    • OKAZAKI KENJI
    • G06F11/00G06F11/07
    • G06F11/073G06F11/0703
    • PURPOSE:To obtain various indication data for processing actions when a computer has a runaway by setting a detection area in response to a non-using area, etc. of a memory space. CONSTITUTION:Address input terminals a0-a9 of a ROM1 are connected to an address bus of a CPU. The output signal of a mode selection switch 3 is supplied to address input terminals a10-a13 respectively of the ROM1. The ROM1 outputs properly an output signal in response to the address received an access. This output signal is decoded by a decoder 7 and supplied to a memory circuit 8. The circuit 8 stores the output signals of both the decoder 7 and a timer 9 and outputs a control signal and an instruction code to the CPU based on the result of storage of the circuit 8.
    • 目的:通过响应于存储空间的不使用区域等设置检测区域来获得计算机失控时的处理动作的各种指示数据。 构成:将ROM1的地址输入端子a0-a9连接到CPU的地址总线。 模式选择开关3的输出信号分别提供给ROM1的地址输入端子a10-a13。 响应于接收到的地址,ROM1正确地输出输出信号。 该输出信号由解码器7解码并提供给存储电路8.电路8存储解码器7和定时器9的输出信号,并根据以下结果输出控制信号和指令码给CPU 存储电路8。
    • 10. 发明专利
    • Memory device for fault analysis
    • 故障分析记忆设备
    • JPS61103252A
    • 1986-05-21
    • JP22558984
    • 1984-10-26
    • Fuji Electric Co Ltd
    • UCHIYAMA SUMIO
    • G06F11/30G06F11/07G06F11/34
    • G06F11/0745G06F11/0703
    • PURPOSE:To reduce the fault analysis load and to secure satisfactory information when a fault occurs by adding a fault analyzing memory device to supply the fault information, etc. through an applied device of a microcomputer. CONSTITUTION:For a microcomputer application device 1, a fault detecting part 12, a main memory part 13, an input/output part 14 and a fault analyzing memory connection part 2 are connected to a CPU11 via an internal bus 16. The CPU1 is connected to the part 12 by an uninhibitable interruption signal (NMi) 17. Then the CPU11 usually executes programs in a normal mode of a control program, etc. on the part 13 and controls an external device D to be controlled via the part 14. If the part 12 detects such a fault as an abnormal parity, the time-up, out-of-area access, etc. while the CPU11 is executing a program, an interruption is applied to the CPU11 by the signal (NMi) 17. Thus the CPU11 knows the fault and executed a fault processing program.
    • 目的:减少故障分析负载,并通过添加故障分析存储器件以通过微机的应用设备提供故障信息等来确保故障发生时的令人满意的信息。 构成:对于微型计算机应用设备1,故障检测部分12,主存储器部分13,输入/输出部分14和故障分析存储器连接部分2经由内部总线16连接到CPU11。CPU1被连接 通过不可阻挡的中断信号(NMi)17到达部分12.然后,CPU11通常在部件13上以控制程序等的正常模式执行程序,并且通过部分14控制外部设备D的控制。如果 当CPU11正在执行程序时,部分12检测到异常奇偶校验,时间上升,超区域访问等故障,通过信号(NMi)17向CPU11施加中断。因此 CPU11知道故障并执行故障处理程序。