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1. 发明专利

JPH08123720A DATA TRANSFER PROCESSOR AND METHOD FOR CONTROLLING DATA TRANSFER 失效
公开(公告)号：JPH08123720A
公开(公告)日：1996-05-17
申请号：JP26491794
申请日：1994-10-28
申请人： FUJITSU LTD
发明人： MURAKAMI TAKESHI , OTAKE TERUO , SUZUKI RYUICHI , MIYAJIMA SHIGERU
IPC分类号： G06F12/02
摘要： PURPOSE: To effectively utilize a page mode of a memory and to attain high speed plotting processing with respect to a data transfer processor and a data transfer controlling method for applying logical operation to data in an optional area of memory space and transferring the data to another area. CONSTITUTION: When an area to be accessed is changed to plural transferring areas and transferred areas, an address decision circuit 14 decides whether the page of an unswitched memory address matches the page of a switched memory address or not, and when both the pages match with each other, page mode access is continued. When both the pages are different from each other, new page mode access is executed.

2. 发明专利

JPS6225359A PROCESSING REQUEST CONTROL SYSTEM FOR INFORMATION PROCESSING SYSTEM 失效
公开(公告)号：JPS6225359A
公开(公告)日：1987-02-03
申请号：JP16455085
申请日：1985-07-25
申请人： FUJITSU LTD
发明人： MIYAJIMA SHIGERU
IPC分类号： G06F13/12 , G06F13/26 , G06F13/362
摘要： PURPOSE:To improve the processing ability of an information processing system by checking the priority of a processing request, carrying out processing according to the priority, and putting it in a queue until a break when the request conflicts. CONSTITUTION:A processor 10 checks the priority by a priority level circuit 101 and performs processing with higher priority when it conflicts. A low processing ability request detecting circuit 102 detects a request from a low processing ability device 12 and sends a request detection signal to a high processing ability device 11 by a request informing circuit 103. the request stop circuit 112 of high processing ability device 11 inhibits a request generating circuit 111 from outputting a processing request according to a signal from a request detecting circuit 103 for a constant time based upon a timing signal after an operation end signal indicating a break of processing being carried out.

3. 发明专利

JPS61114352A Channel address conversion system 失效
标题翻译：通道地址转换系统
公开(公告)号：JPS61114352A
公开(公告)日：1986-06-02
申请号：JP23472984
申请日：1984-11-07
申请人： Fujitsu Ltd
发明人： MIYAJIMA SHIGERU , KANEKO KENICHI , AKASAKA TSUTOMU
IPC分类号： G06F12/10 , G06F13/12
摘要： PURPOSE: To cope with high-speed transfer of data on an I/O and also to avoid the generation of an overrun, etc., by performing the address conversion of high speed equivalent to a TLB (translation look-aside buffer) at the channel side and therefore increasing the number of channels.
CONSTITUTION: A channel data processor CDP is provided between a main memory MM and a channel CH. The memory MM contains a logical/real address conversion table TB, and the CDP contains a conversion mechanism TM corresponding to a TLB. Four conversion registers are provided to each channel of the mechanism TM to store the result of conversion between a logical address and a real address. A subchannel memory SCM contains a storage area SR for result of conversion. Thus the results of logical/real address conversions of the mechanism TM are stored to the area SR for each subchannel.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：为了应对I / O上的高速数据传输，并且通过执行相当于TLB（转换后备缓冲器）的高速地址转换来避免产生超限等通道侧，因此增加通道数。构成：在主存储器MM和通道CH之间提供通道数据处理器CDP。存储器MM包含逻辑/真实地址转换表TB，并且CDP包含对应于TLB的转换机制TM。四个转换寄存器被提供给机构TM的每个通道以存储逻辑地址和实际地址之间的转换结果。子通道存储器SCM包含用于转换结果的存储区域SR。因此，机制TM的逻辑/实际地址转换的结果被存储到每个子信道的区域SR。

4. 发明专利

JPS6158069A Data processing device 失效
标题翻译：数据处理设备
公开(公告)号：JPS6158069A
公开(公告)日：1986-03-25
申请号：JP16525584
申请日：1984-08-07
申请人： Fujitsu Ltd
发明人： MIYAJIMA SHIGERU
IPC分类号： G06F13/12 , G06F13/362
CPC分类号： G06F13/122 , G06F13/362
摘要： PURPOSE:To operate all channel devices on the average and to enhance processing capacity of a data processing device and transfer capacity of a two-way bus by installing a priority order control circuit at the data processing device having the first priority order circuit of a two-way bus. CONSTITUTION:At a priority order circuit 11' for a two-way bus 3 of a channel control device 1, a circuit is installed which detects a data transfer request signal from the channel device when a response can be continuosly executed for the channel devices CH0-CHn. When the circuit detects a new data transfer request, a priority order control circuit 14 can send the new transfer request from channel devices CH0-CHn to the two-way bus 3 and after that, the next response is executed by the other channel.
摘要翻译：目的：平均操作所有通道设备，并通过在具有两个总线的第一优先级顺序电路的数据处理设备上安装优先级顺序控制电路来增强数据处理设备的处理能力和传输双向总线的容量 - 公车。构成：在通道控制装置1的双向总线3的优先顺序电路11'上，安装有可以对通道装置CH0连续执行响应时从信道装置检测数据传送请求信号的电路 -CHn。当电路检测到新的数据传输请求时，优先顺序控制电路14可以将新的传送请求从信道设备CH0-CHn发送到双向总线3，之后由另一个信道执行下一个响应。

5. 发明专利

JPS6049439A CONTROL SYSTEM OF MICROPROGRAM 失效
公开(公告)号：JPS6049439A
公开(公告)日：1985-03-18
申请号：JP15738583
申请日：1983-08-29
申请人： FUJITSU LTD
发明人： MIYAJIMA SHIGERU
IPC分类号： G06F9/28 , G06F9/22 , G06F9/38
摘要： PURPOSE:To increase the executing speed of a move instruction by controlling a microstep so as to by-pass when it is detected that an instruction following the move instruction is fetched. CONSTITUTION:An instruction which is under execution is stored to an instruction buffer register 630, and the instruction to be executed next is prefetched and also stored to an instruction buffer register 620. If the corresponding instruction is equal to a move instruction, furthermore the following instruction is prefetched from a main memory and stored to an instruction buffer register 610. Then a valid bit 611 is turned on. Under such a condition, an operation part OPC of the register 620 is fed to a decoder DEC64. Then a signal line showing the move instruction, etc. is energized and receives an AND through a logical circuit 65 together with the ON signal of the bit 611. Thus NO-IFETCH signal is outputted. As a result, an OP code branch plus an N-bit branch are executed and a branch to a step 3 from a step 1 is executed.

6. 发明专利

JPS59176851A Data storing system 失效
标题翻译：数据存储系统
公开(公告)号：JPS59176851A
公开(公告)日：1984-10-06
申请号：JP5077483
申请日：1983-03-27
申请人： Fujitsu Ltd
发明人： MARUO AKIHIRO , MIYAJIMA SHIGERU
IPC分类号： G06F9/30 , G06F11/14
CPC分类号： G06F11/14
摘要： PURPOSE:To shorten the data processing time by storing the data immediately to a local storage with no special checking and performing the prescribed processing after detecting a specific bit train for retrial. CONSTITUTION:Output lines L1-L4 are controlled to perform writing to a local storage DSLS for each fetching. An output line L2 of an aligning direction register ALR is stored while giving distinction to the fetching outputs between the 1st and 2nd cycles. In the 1st cycle the normal aligning direction data is stored; while the aligning direction is stored in the form of a specific bit string in the 2nd cycle. Then the different direction from the storage is applied for reading, and the data detected said specific bit string is stored in a main memory MS after a logical operation performed with the cycle data to be read out next. An address register ADR is added together with a data length register DLR and a data aligning circuit DAL.
摘要翻译：目的：通过在没有特别检查的情况下立即将数据存储到本地存储器，并在检测到特定的位列进行重试后执行规定的处理来缩短数据处理时间。规定：输出线L1-L4被控制以对每次取出执行写入本地存储DSLS。存储对齐方向寄存器ALR的输出线L2，同时对第1和第2周期之间的取出输出进行区分。在第一循环中存储正常对准方向数据; 而对齐方向在第二周期中以特定位串的形式存储。然后，将与存储器不同的方向应用于读取，并且在用随后读取的周期数据执行逻辑操作之后，检测到的所述特定位串的数据被存储在主存储器MS中。地址寄存器ADR与数据长度寄存器DLR和数据对准电路DAL相加。

7. 发明专利

JPS5856541A ADDRESS CONTROLLING SYSTEM 失效
公开(公告)号：JPS5856541A
公开(公告)日：1983-04-04
申请号：JP15501481
申请日：1981-09-30
申请人： FUJITSU LTD
发明人： MIYAJIMA SHIGERU
IPC分类号： G01M11/00 , G01R31/11 , G06F9/30 , G06F9/32 , H04B17/00
摘要： PURPOSE:To reduce the number of circuit components and to improve the processing speed, by unifying address updating control circuits which reads out instructions and operands and writes them. CONSTITUTION:At instruction readout, an instruction address is stored in a main storage address register circuit 2 from an address storage circuit 4 and a revised amount of the instruction address is formed in an instruction readout storage address updating control circuit 5. An updating signal 11 updates the address of an address updating circuit 3 and the instruction address is stored in the circuit 4. At readout/write of operands, the amount of updating of the operand address is formed in an operand readout/write storage address updating control circuit 6. When the amount of access of operands such as MOVE instruction and the like is much, the control is taken over from the circuit 6 to the circuit 5 with a signal 13 to update the operand address of the circuit 4 through the signal 11 via the circuit 3 for the updated amount of the initial access.

8. 发明专利

JPS57197660A REGISTER SAVE SYSTEM 失效
公开(公告)号：JPS57197660A
公开(公告)日：1982-12-03
申请号：JP8206581
申请日：1981-05-29
申请人： FUJITSU LTD
发明人： MIYAJIMA SHIGERU , MARUO AKIHIRO
IPC分类号： G06F12/00 , G06F9/34 , G06F12/08
摘要： PURPOSE:To reduce the number of circuits, by commonly using a copy register for tentative evacuation as to memory access information when the memory access is at non-hit state, together with other registers. CONSTITUTION:A memory access circuit of a CPU controls the memory access from a channel accompanied with data transfer with priority. As to the memory access information when the memory access is at non-hit (NONHIT) state, a copy register 3 with tentative evacuation is commonly used with a register saving the memory access information of the CPU subjected to interference with the memory access from the channel.

9. 发明专利

JPH02135393A DISPLAY DEVICE 失效
公开(公告)号：JPH02135393A
公开(公告)日：1990-05-24
申请号：JP28953788
申请日：1988-11-16
申请人： FUJITSU LTD
发明人： ADACHI TOMOSHIGE , USHIWAKA KEIICHI , MIYAJIMA SHIGERU , MUNAKATA AKIO
IPC分类号： G06F3/153 , G09G5/06 , G09G5/36 , G09G5/38
摘要： PURPOSE:To simply and cheaply constitute a display control part by providing a frame buffer between the display control part and a display part. CONSTITUTION:The title device is provided with a memory 1 which stores patterns to be displayed and color converting table every pattern, the frame buffer 3, the display control part 2 which draws out the color converting tables of the pattern to be displayed from the memory 1, converts the color of the patterns to be displayed, and writes into the frame buffer 3, and the display part 5 which displays the contents. That is, since the frame buffer 3 is provided between the display control part 2 and the display part 5, there is no need for color development by video rate during one horizontal scanning. Besides, there is no need for providing color converting table of all patterns in the display control part 2. Thus, storage elements for the color converting table of the display control part 2 is reduced and the title device can be miniaturized and its cost can be reduced.

10. 发明专利

JPS61147337A MICROPROGRAM CONTROL SYSTEM 失效
公开(公告)号：JPS61147337A
公开(公告)日：1986-07-05
申请号：JP26925484
申请日：1984-12-20
申请人： FUJITSU LTD
发明人： MIYAJIMA SHIGERU
IPC分类号： G06F9/22 , G06F9/26
摘要： PURPOSE:To attain high speed trap processing by providing a trap address register and saving a microprogram address for the processing executed next at generation of response waiting. CONSTITUTION:When a response wait is generated, a microprogram issues a link return order to save a microprogram address for the processing executed next set to a CSAR13 to a CS address area of the entry of corresponding channel of a trap address register (TAR) 16 via a gate G4. When a response comes from an external device, a channel trap is generated and its channel number is set to a CHNR17. The TAR16 is searched according to the number, and when a bad bit of the entry coincident to the channel number is set, a CS address of the CS address area of the entry is read and set to the CSAR13 through a gate G6.

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